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公开(公告)号：US11183503B2
公开(公告)日：2021-11-23
申请号：US16663952
申请日：2019-10-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Chih-Hsiang Chang , Fu-Chen Chang
IPC: H01L27/11502 , H01L27/11507 , H01L49/02 , G11C11/22 , H01L27/11504
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.
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公开(公告)号：US20200335694A1
公开(公告)日：2020-10-22
申请号：US16910609
申请日：2020-06-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.
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公开(公告)号：US10510953B2
公开(公告)日：2019-12-17
申请号：US16372642
申请日：2019-04-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.
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公开(公告)号：US10276790B2
公开(公告)日：2019-04-30
申请号：US15715413
申请日：2017-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
Abstract: Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess.
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公开(公告)号：US10008662B2
公开(公告)日：2018-06-26
申请号：US14645683
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Chun You , Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L21/336 , H01L43/08 , H01L43/12 , H01L27/22
CPC classification number: H01L43/08 , G11C11/16 , H01L27/228 , H01L43/12
Abstract: A method of forming a magnetoresistive random access memory (MRAM) device including a perpendicular MTJ (magnetic tunnel junction) is provided. The method includes forming a magnetic tunneling junction (MTJ) over a bottom electrode layer. A top electrode layer is formed over an upper surface of the MTJ, and a hard mask is formed over an upper surface of the top electrode layer. A first etch is performed through the top electrode layer, through regions of the MTJ unmasked by the hard mask, to form a top electrode and an etched MTJ. Sidewall spacers are formed extending from an upper surface of the hard mask or the top electrode, along sidewalls of the top electrode and the etched MTJ, to a point below or about even with an upper surface of the bottom electrode. A resulting MRAM device structure is also provided.
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Patent Agency Ranking
公开(公告)号：US20180012657A1
公开(公告)日：2018-01-11
申请号：US15702136
申请日：2017-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sheng-Hung Shih , Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Jen-Sheng Yang , Wen-Ting Chu , Yu-Wen Liao
CPC classification number: H01L45/1273 , G11C13/003 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0083 , G11C2213/79 , H01L27/2427 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.
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公开(公告)号：US09773552B2
公开(公告)日：2017-09-26
申请号：US15399977
申请日：2017-01-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sheng-Hung Shih , Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Jen-Sheng Yang , Wen-Ting Chu , Yu-Wen Liao
CPC classification number: H01L45/1273 , G11C13/003 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0083 , G11C2213/79 , H01L27/2427 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by forming an initial conductive filament within a dielectric data storage layer of an RRAM cell having a bottom electrode connected to a drain terminal of a PMOS transistor and a top electrode separated from the bottom electrode by the dielectric data storage layer. The initial conductive filament is formed by turning on the PMOS transistor by providing a substantially zero first forming voltage to a gate terminal of the PMOS transistor, by providing a substantially zero second forming voltage to a source terminal of the PMOS transistor, by providing a first non-zero forming voltage to a bulk terminal of the PMOS transistor, and by providing a second non-zero forming voltage to the top electrode.
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48.发明申请PERPENDICULAR MAGNETIC TUNNELING JUNCTION (MTJ) FOR IMPROVED MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) PROCESS 有权用于改进磁阻随机存取存储器（MRAM）过程的全面磁通隧道（MTJ）公开(公告)号：US20160268499A1
公开(公告)日：2016-09-15
申请号：US14645683
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Chun You , Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Ting Chu , Yu-Wen Liao
CPC classification number: H01L43/08 , G11C11/16 , H01L27/228 , H01L43/12
Abstract: A method of forming a magnetoresistive random access memory (MRAM) device including a perpendicular MTJ (magnetic tunnel junction) is provided. The method includes forming a magnetic tunneling junction (MTJ) over a bottom electrode layer. A top electrode layer is formed over an upper surface of the MTJ, and a hard mask is formed over an upper surface of the top electrode layer. A first etch is performed through the top electrode layer, through regions of the MTJ unmasked by the hard mask, to form a top electrode and an etched MTJ. Sidewall spacers are formed extending from an upper surface of the hard mask or the top electrode, along sidewalls of the top electrode and the etched MTJ, to a point below or about even with an upper surface of the bottom electrode. A resulting MRAM device structure is also provided.
Abstract translation: 提供了一种形成包括垂直MTJ（磁性隧道结）的磁阻随机存取存储器（MRAM）装置的方法。 该方法包括在底部电极层上形成磁性隧道结（MTJ）。 在MTJ的上表面上形成顶部电极层，并且在顶部电极层的上表面上形成硬掩模。 通过顶部电极层，通过未被掩模掩模的MTJ的区域进行第一蚀刻，以形成顶部电极和蚀刻的MTJ。 从硬掩模或顶部电极的上表面，沿着顶部电极和蚀刻的MTJ的侧壁延伸到下部或大致甚至与底部电极的上表面相连的侧壁间隔物。 还提供了所产生的MRAM器件结构。
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公开(公告)号：US09172036B2
公开(公告)日：2015-10-27
申请号：US14087082
申请日：2013-11-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
CPC classification number: H01L45/1233 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1666 , H01L45/1683
Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.
Abstract translation: 一种包括在衬底上形成的电阻随机存取存储器（RRAM）单元的集成电路器件。 RRAM单元包括具有上表面的顶电极。 阻挡层覆盖上表面的一部分。 通孔在电介质矩阵内在顶部电极上方延伸。 顶部电极的上表面包括与阻挡层接触的区域和与通孔相接合的区域。 与通孔相接的上表面的区域围绕与阻挡层相接的上表面区域。 阻挡层在处理期间是功能性的，以保护RRAM单元免受蚀刻损伤，同时以不妨碍上覆通孔和顶部电极之间的接触的方式构造。
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公开(公告)号：US12114509B2
公开(公告)日：2024-10-08
申请号：US17712495
申请日：2022-04-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
CPC classification number: H10B53/30 , G11C11/221 , H01L28/56 , H01L28/75 , H10B53/10
Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
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