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公开(公告)号：US20210350836A1
公开(公告)日：2021-11-11
申请号：US16870220
申请日：2020-05-08
Inventor： Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
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公开(公告)号：US09424917B2
公开(公告)日：2016-08-23
申请号：US13788063
申请日：2013-03-07
Inventor： Chih-Yang Chang , Wen-Ting Chu , Chia-Fu Lee
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/0097 , G11C2213/79
Abstract: Methods for operating memory are disclosed. A method includes applying a select word line voltage to a word line node of a first resistive random access memory (RRAM) cell; applying a first programming voltage to a source line node of the first RRAM cell; and setting the first RRAM cell comprising applying a second programming voltage to a bit line node of the first RRAM cell. The first programming voltage is greater than zero volts, and the second programming voltage is greater than the first programming voltage. Other disclosed methods include concurrently setting and resetting RRAM cells.
Abstract translation: 公开了操作存储器的方法。 一种方法包括：将选择字线电压施加到第一电阻随机存取存储器（RRAM）单元的字线节点; 将第一编程电压施加到所述第一RRAM单元的源极线节点; 以及设置所述第一RRAM单元包括将第二编程电压施加到所述第一RRAM单元的位线节点。 第一编程电压大于零伏，第二编程电压大于第一编程电压。 其他公开的方法包括同时设置和重置RRAM单元。
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公开(公告)号：US20250119060A1
公开(公告)日：2025-04-10
申请号：US18483769
申请日：2023-10-10
Inventor： Cheng Han Lu , Chia-Fu Lee , Yen-An Chang
IPC: H02M3/07 , G11C11/413
Abstract: A circuit is disclosed. The circuit includes a first pump circuit configured to receive a first reference voltage and provide an output voltage at a first level based on the first reference voltage. The circuit includes a second pump circuit configured to receive a second reference voltage and provide the output voltage at a second level based on the second reference voltage. The first reference voltage is lower than the second reference voltage, and the first level is lower than the second level.
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公开(公告)号：US20250078921A1
公开(公告)日：2025-03-06
申请号：US18954783
申请日：2024-11-21
Inventor： Po-Hao Lee , Chia-Fu Lee , Yi-Chun Shih
IPC: G11C13/00
Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
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公开(公告)号：US12217819B2
公开(公告)日：2025-02-04
申请号：US17656425
申请日：2022-03-25
Inventor： Yu-Der Chih , Chia-Fu Lee
IPC: G11C7/10 , G11C7/12 , G11C8/08 , G11C11/4074
Abstract: A method for performing an in-memory computation includes: storing data in memory cells of a memory array, the data including weights for computation; determining whether an update command to change at least one of the weights is received; in response to receiving the update command, performing a write operation on the memory array to update the at least one weight; and disabling the write operation on the memory array until receiving a next update command to change the at least one weight.
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Patent Agency Ranking
公开(公告)号：US12164882B2
公开(公告)日：2024-12-10
申请号：US17203130
申请日：2021-03-16
Inventor： Yu-Der Chih , Hidehiro Fujiwara , Yi-Chun Shih , Po-Hao Lee , Yen-Huei Chen , Chia-Fu Lee , Jonathan Tsung-Yung Chang
IPC: G06F7/501 , G06F7/53 , G11C7/10 , G11C11/4074
Abstract: A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements.
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公开(公告)号：US20240385802A1
公开(公告)日：2024-11-21
申请号：US18469879
申请日：2023-09-19
Inventor： Yu-Der Chih , Chia-Fu Lee , Jonathan Tsung-Yung Chang
Abstract: A computing-in-memory circuit includes an input circuit to receive a number (N) of input pairs, each of the N input pairs comprising a first one and a second one of N exponents, and a first one and a second one of N mantissas; a first adder circuit to generate N exponent sums based on the first and second exponents of the N input pairs; a subtractor circuit configured to calculate N exponent differences, each of the N exponent differences being equal to a difference between a corresponding one of the N exponent sums and a largest one of the N exponent sums; and a comparator circuit to compare each of the N exponent differences with a threshold to generate N control signals. N mantissa products of the first and second mantissas of the N input pairs, respectively, are to be selectively combined based on the N control signals.
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公开(公告)号：US20240170031A1
公开(公告)日：2024-05-23
申请号：US18424164
申请日：2024-01-26
Inventor： Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
CPC classification number: G11C7/08 , G11C7/067 , G11C7/1039 , G11C11/1673 , G11C29/42
Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
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公开(公告)号：US11973502B2
公开(公告)日：2024-04-30
申请号：US18310143
申请日：2023-05-01
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
IPC: H03K3/356
CPC classification number: H03K3/35613
Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.
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公开(公告)号：US20230268909A1
公开(公告)日：2023-08-24
申请号：US18310143
申请日：2023-05-01
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
IPC: H03K3/356
CPC classification number: H03K3/35613
Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.
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