-
公开(公告)号：US20160181198A1
公开(公告)日：2016-06-23
申请号：US14971402
申请日：2015-12-16
发明人： DAEIK KIM , Jemin Park , Sunghee Han , Yoosang Hwang
IPC分类号： H01L23/522 , H01L29/06 , H01L27/108
CPC分类号： H01L23/5223 , H01L23/5226 , H01L27/10814 , H01L27/10817 , H01L27/10855 , H01L27/10897 , H01L29/4236 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.
摘要翻译： 半导体器件包括第一器件隔离区和限定衬底中的第一有源区，第二有源区和第三有源区的第二器件隔离区，暴露第一有源区的上表面的凹陷区和上表面 的第一和第二器件隔离区域以及第二和第三有效区域上的主动缓冲器图案。 第一有源区位于第二和第三有源区之间，第一器件隔离区位于第一和第二有源区之间，第二器件隔离区位于第一和第三有源区之间。 第二和第三有源区域的上侧壁在凹陷区域中露出。
-
公开(公告)号：US12069849B2
公开(公告)日：2024-08-20
申请号：US18124043
申请日：2023-03-21
发明人： Daeik Kim , Bong-Soo Kim , Jemin Park , Taejin Park , Yoosang Hwang
IPC分类号： H10B12/00 , H01L21/3213 , H01L21/768 , H01L21/8234 , H01L29/66
CPC分类号： H10B12/482 , H01L21/3213 , H01L21/76829 , H01L21/76838 , H01L21/823468 , H01L29/6656 , H10B12/033 , H10B12/053 , H10B12/31 , H10B12/315 , H10B12/34
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.
-
公开(公告)号：US11610896B2
公开(公告)日：2023-03-21
申请号：US17245203
申请日：2021-04-30
发明人： Daeik Kim , Bong-Soo Kim , Jemin Park , Taejin Park , Yoosang Hwang
IPC分类号： H01L27/108 , H01L21/768 , H01L29/66 , H01L21/3213
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.
-
公开(公告)号：US11610891B2
公开(公告)日：2023-03-21
申请号：US17725806
申请日：2022-04-21
发明人： Jaehwan Cho , Junghwan Oh , Sangho Lee , Junwon Lee , Jinwoo Bae , Sunghee Han , Yoosang Hwang
IPC分类号： H01L27/108
摘要： A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.
-
公开(公告)号：US20220278121A1
公开(公告)日：2022-09-01
申请号：US17748261
申请日：2022-05-19
发明人： Kiseok Lee , Junsoo Kim , Hui-Jung Kim , Bong-Soo Kim , Satoru Yamada , Kyupil Lee , Sunghee Han , HyeongSun Hong , Yoosang Hwang
IPC分类号： H01L27/11556 , H01L23/532 , G11C7/18 , H01L49/02 , G11C8/14 , H01L27/11524
摘要： A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.
-
公开(公告)号：US11348996B2
公开(公告)日：2022-05-31
申请号：US16860136
申请日：2020-04-28
发明人： Jae-Hwan Cho , Sangho Lee , Yoosang Hwang
IPC分类号： H01L49/02 , H01L27/108 , H01L27/02
摘要： Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.
-
公开(公告)号：US20220130950A1
公开(公告)日：2022-04-28
申请号：US17568780
申请日：2022-01-05
发明人： Jae-Hwan Cho , Sangho Lee , Yoosang Hwang
IPC分类号： H01L49/02 , H01L27/108 , H01L27/02
摘要： Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.
-
公开(公告)号：US20220068859A1
公开(公告)日：2022-03-03
申请号：US17207242
申请日：2021-03-19
发明人： Hyungeun Choi , Eun-Ji Kim , Jong-Ho Moon , Hyoungyol Mun , Han-Sik Yoo , Kiseok Lee , Seungjae Jung , Taehyun An , Sangyeon Han , Yoosang Hwang
IPC分类号： H01L23/00 , H01L27/108 , G11C11/408 , G11C11/4091 , H01L25/065 , H01L25/18
摘要： A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.
-
公开(公告)号：US20220028860A1
公开(公告)日：2022-01-27
申请号：US17192084
申请日：2021-03-04
发明人： Minsu Choi , Myeong-Dong Lee , Hyeon-Woo Jang , Keunnam Kim , Sooho Shin , Yoosang Hwang
IPC分类号： H01L27/108
摘要： Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.
-
公开(公告)号：US11195836B2
公开(公告)日：2021-12-07
申请号：US16732925
申请日：2020-01-02
发明人： Hui-Jung Kim , Min Hee Cho , Junsoo Kim , Taehyun An , Dongsoo Woo , Yoosang Hwang
IPC分类号： H01L27/108 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02
摘要： A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.
-
-
-
-
-
-
-
-
-
搜索结果
124 条记录 (耗时 0.029 秒)
