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    Semiconductor device
    41.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10706902B2

    公开(公告)日：2020-07-07

    申请号：US16192272

    申请日：2018-11-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro Ishii

    IPC: G11C8/16 ,  G11C11/408 ,  G11C8/08 ,  G11C11/417 ,  G11C7/10 ,  H01L27/11 ,  G11C8/14 ,  G11C7/12 ,  G11C11/419 ,  G11C7/02 ,  G11C5/06

    Abstract: A semiconductor device includes: memory cells, first word lined arranged for first ports and each arranging corresponding to respective rows of the memory cells; second word lines arranged for second ports and each arranged corresponding to respective rows of the memory cells, first dummy word lines each provided above the respective first word lines, second dummy word lines each provided above the respective second word lines, a word line driver driving the first and second word lines, and a dummy word line driver driving, in an opposite phase, the second dummy word line for the adjacent second word line according to driving of the first word line from among the first and second word lines, or the first dummy word line for the adjacent first word line according to driving of the second word line from among the first and second word lines.

    Multiport memory, memory macro and semiconductor device
    42.
    发明授权
    Multiport memory, memory macro and semiconductor device 有权

    公开(公告)号：US10460795B2

    公开(公告)日：2019-10-29

    申请号：US16214220

    申请日：2018-12-10

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii ,  Makoto Yabuuchi ,  Masao Morimoto

    IPC: G11C11/00 ,  G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C8/08 ,  G11C8/06

    Abstract: A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.

    SEMICONDUCTOR DEVICE
    44.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190198499A1

    公开(公告)日：2019-06-27

    申请号：US16287570

    申请日：2019-02-27

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto YABUUCHI ,  Yuichiro Ishii

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528

    CPC classification number: H01L27/0924 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823892 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0928

    Abstract: A semiconductor device includes a semiconductor substrate, a first well region formed on the semiconductor substrate, a first fin integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view, a first electrode formed on the first fin via a first gate insulating film, and extended in a second direction crossing the first direction in the plan view, a tap region formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential to the first well region, a second fin integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view, and a first wiring layer formed on the second fin in a portion overlapping the tap region in the plan view.

    Semiconductor storage device
    45.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US10068641B2

    公开(公告)日：2018-09-04

    申请号：US15894757

    申请日：2018-02-12

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii

    IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14

    CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C7/12 ,  G11C2207/2227

    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

    Multi-port memory and semiconductor device
    46.
    发明授权
    Multi-port memory and semiconductor device 有权

    公开(公告)号：US10026472B2

    公开(公告)日：2018-07-17

    申请号：US15674659

    申请日：2017-08-11

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii

    IPC: G11C11/00 ,  G11C11/418 ,  G11C11/419

    Abstract: In a multi-port memory, a first pulse signal generator circuit generates a first pulse signal following input of a clock signal. A first latch circuit sets a first start signal to a first state in response to generation of the first pulse signal, and resets the first start signal to a second state in response to a first delayed signal obtained by delaying the first start signal by a delay circuit. A second pulse signal generator circuit generates a second pulse signal following input of the first delayed signal. A first latch circuit sets a second start signal to the first state and holds this state in response to generation of the second pulse signal, and resets the second start signal to the second state in response to a second delayed signal obtained by delaying the second start signal by the delay circuit. The memory operates based on start signals.

    Semiconductor memory device
    48.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US09798600B2

    公开(公告)日：2017-10-24

    申请号：US14868238

    申请日：2015-09-28

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Yoshikazu Saito

    IPC: G11C29/00 ,  G06F11/07

    CPC classification number: G06F11/0751 ,  G06F11/073

    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

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