公开(公告)号：US20050221623A1

公开(公告)日：2005-10-06

申请号：US11136845

申请日：2005-05-25

申请人： Matthias Passlack ,  Nicholas Medendorp

发明人： Matthias Passlack ,  Nicholas Medendorp

IPC分类号： C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/28 ,  H01L21/31 ,  H01L21/316 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/513 ,  C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/02112 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/28194 ,  H01L21/28264 ,  H01L21/31604 ,  H01L21/31666 ,  H01L29/4232 ,  H01L29/511 ,  H01L29/517

摘要： A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the Ga—Gd-oxide provides a low oxide leakage current density.

公开(公告)号：US5550089A

公开(公告)日：1996-08-27

申请号：US217332

申请日：1994-03-23

申请人： Niloy K. Dutta ,  Russell J. Fischer ,  Neil E. J. Hunt ,  Matthias Passlack ,  Erdmann F. Schubert ,  George J. Zydzik

发明人： Niloy K. Dutta ,  Russell J. Fischer ,  Neil E. J. Hunt ,  Matthias Passlack ,  Erdmann F. Schubert ,  George J. Zydzik

IPC分类号： C23C14/08 ,  H01L29/51 ,  H01L31/04 ,  H01L33/44 ,  H01S5/00 ,  H01S5/028 ,  H01L21/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/463

CPC分类号： H01L29/517 ,  C23C14/08 ,  H01L33/44 ,  H01S5/028

摘要： An optoelectronic lII-V or II-VI semiconductor device comprises a thin film coating with optical characteristics providing low midgap interface state density. A field effect device for inversion channel applications on III-V semiconductors also comprises a thin dielectric film providing required interface characteristics. The thin film is also applicable to passivation of states on exposed surfaces of electronic III-V devices. The thin film comprises a uniform, homogeneous, dense, stoichiometric gallium oxide (Ga.sub.2 O.sub.3) dielectric thin film, fabricated by electron-beam evaporation of a single crystal, high purity Gd.sub.3 Ga.sub.5 O.sub.12 complex compound on semiconductor substrates kept at temperatures ranging from 40.degree. to 370.degree. C. and at background pressures at or above 1.times.10.sup.-10 Torr.

摘要翻译： 光电子II-V或II-VI半导体器件包括具有提供低中间界面态密度的光学特性的薄膜涂层。 用于III-V半导体上的反向沟道应用的场效应器件还包括提供所需接口特性的薄电介质膜。 薄膜也适用于电子III-V器件暴露表面的状态钝化。 该薄膜包括均匀，均匀，致密的化学计量的氧化镓（Ga 2 O 3）电介质薄膜，其通过在保持在40℃至370℃的温度范围内的半导体衬底上的单晶，高纯度Gd 3 Ga 5 O 12络合物的电子束蒸发 在背景压力为1×10-10乇或以上。

公开(公告)号：US08735903B2

公开(公告)日：2014-05-27

申请号：US12974775

申请日：2010-12-21

申请人： Matthias Passlack

发明人： Matthias Passlack

IPC分类号： H01L29/15

CPC分类号： H01L29/7783 ,  H01L21/823807 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/517 ,  H01L29/7781

摘要： Layer structures for use in density of states (“DOS”) engineered FETs are described. One embodiment comprises a layer structure for use in fabricating an n-channel transistor. The layer structure includes a first semiconductor layer having a conduction band minimum EC1; a second semiconductor layer having a discrete hole level H0; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer; wherein the discrete hole level H0 is positioned below the conduction band minimum Ec1 for zero bias applied to the gate metal layer.

摘要翻译： 描述了用于状态密度（“DOS”）工程化FET的层结构。 一个实施例包括用于制造n沟道晶体管的层结构。 层结构包括具有导带最小EC1的第一半导体层; 具有离散孔级H0的第二半导体层; 布置在第一和第二半导体层之间的宽带隙半导体阻挡层; 设置在所述第一半导体层上方的栅介质层; 以及栅极金属层，其设置在所述栅极介电层的上方; 其中离散孔电平H0位于施加到栅极金属层的零偏压的导带最小值Ec1之下。

公开(公告)号：US20110193092A1

公开(公告)日：2011-08-11

申请号：US12974954

申请日：2010-12-21

申请人： Matthias Passlack

发明人： Matthias Passlack

IPC分类号： H01L29/205

CPC分类号： H01L29/7787 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/088 ,  H01L27/092 ,  H01L29/122 ,  H01L29/155 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/517 ,  H01L29/7783 ,  H01L31/03046 ,  H01L31/035236 ,  H01L31/1844

摘要： A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H0; a second semiconductor layer having a conduction band minimum EC2; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level H0 below the conduction band minimum Ec2 for zero bias applied to the gate metal layer and to obtain n-terminal characteristics.

摘要翻译： 描述了一个单端晶体管器件。 在一个实施例中，n沟道晶体管包括具有离散孔级H0的第一半导体层; 具有导带最小EC2的第二半导体层; 布置在第一和第二半导体层之间的宽带隙半导体阻挡层; 设置在所述第一半导体层上方的栅介质层; 以及栅极金属层，其设置在所述栅极介电层上方并且具有选择的有效功函数以将所述离散孔电平H0定位在所述导带最小值Ec2以下，以将零偏压施加到所述栅极金属层并获得n端子特性。

公开(公告)号：US20110156051A1

公开(公告)日：2011-06-30

申请号：US13042948

申请日：2011-03-08

申请人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

发明人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

IPC分类号： H01L29/20 ,  H01L21/28 ,  H01L29/772

CPC分类号： H01L21/28581 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7787

摘要： Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

摘要翻译： 实施例包括具有低泄漏肖特基接触的半导体器件。 通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。 在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。 使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。 通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

公开(公告)号：US20110068368A1

公开(公告)日：2011-03-24

申请号：US12562852

申请日：2009-09-18

申请人： Matthias Passlack

发明人： Matthias Passlack

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L27/0207 ,  H01L21/02381 ,  H01L21/02521 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/8258 ,  H01L27/0605

摘要： A semiconductor device comprising a honeycomb heteroepitaxy and method for making same are described. One embodiment is a method comprising defining a mask on a silicon substrate, the mask comprising a plurality of nano-size openings therethrough; subsequent to the defining, creating essentially defect-free non-silicon semiconductor nano-islands on portions of a surface of the silicon substrate exposed through the mask openings; subsequent to the creating, depositing high-k gate dielectric is deposited on the nano-islands; and subsequent to the deposition, constructing transistors on the nano-islands.

摘要翻译： 描述了包括蜂窝异质外延的半导体器件及其制造方法。 一个实施例是一种方法，包括在硅衬底上限定掩模，所述掩模包括穿过其中的多个纳米尺寸的开口; 在定义之后，在通过掩模开口暴露的硅衬底的表面的部分上产生基本上无缺陷的非硅半导体纳米岛; 在生成之后，沉积高k栅极电介质沉积在纳米岛上; 并且在沉积之后，在纳米岛上构建晶体管。

公开(公告)号：US20090189252A1

公开(公告)日：2009-07-30

申请号：US12022942

申请日：2008-01-30

申请人： Matthias Passlack ,  Jonathan K. Abrokwah ,  Karthik Rajagopalan ,  Haiping Zhou ,  Richard J. Hill ,  Xu Li ,  David A. Moran ,  Iain G. Thayne ,  Peter Zurcher

发明人： Matthias Passlack ,  Jonathan K. Abrokwah ,  Karthik Rajagopalan ,  Haiping Zhou ,  Richard J. Hill ,  Xu Li ,  David A. Moran ,  Iain G. Thayne ,  Peter Zurcher

IPC分类号： H01L21/334 ,  H01L29/20

CPC分类号： H01L29/78 ,  H01L29/20 ,  H01L29/66462 ,  H01L29/7785

摘要： A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

摘要翻译： 半导体制造工艺包括形成覆盖在包括III-V半导体化合物的衬底（101）上的栅极电介质层（120）。 栅极介电层被图案化以产生具有基本上垂直的侧壁（127）的栅极电介质结构（121），例如大约45°至90°的斜率。 金属接触结构（130）形成在晶片衬底上。 接触结构被充分地从栅极电介质结构侧向移位以限定两者之间的间隙（133）。 对晶片（100）进行热处理，这导致至少一种金属元素迁移，从而在下面的晶片衬底中形成合金区域（137）。 合金区域位于接触结构的下面，并且延伸穿过位于间隙下方的晶片衬底的全部或一部分。 然后形成绝缘或介电覆盖层（140,150），覆盖晶片并覆盖由间隙暴露的衬底的部分。

公开(公告)号：US20090146191A1

公开(公告)日：2009-06-11

申请号：US11950820

申请日：2007-12-05

申请人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

发明人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

IPC分类号： H01L29/00 ,  H01L21/338

CPC分类号： H01L21/28581 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7787

摘要： Method and apparatus are described for semiconductor devices. The method (100) comprises, providing a partially completed semiconductor device (31-1) including a substrate (21), a semiconductor (22) on the substrate (21) and a passivation layer (25) on the semiconductor (22), and using a first mask (32), locally etching the passivation layer (25) to expose a portion (36) of the semiconductor (22), and without removing the first mask (32) forming a Schottky contact (42-1) of a first material on the exposed portion (36) of the semiconductor (22), then removing the first mask (32) and using a further mask (44), forming a step-gate conductor (48-1) of a second material electrically coupled to the Schottky contact (42-1) and overlying parts (25-1) of the passivation layer (25) adjacent to the Schottky contact (42-1). By minimizing the process steps between opening the Schottky contact window (35) in the passivation layer (25) and forming the Schottky contact (42-1) material in this window (35), the gate leakage of a resulting field effect device (51-5) having a Schottky gate (42-1) is substantially reduced.

摘要翻译： 半导体器件描述了方法和装置。 方法（100）包括提供包括衬底（21）的部分完成的半导体器件（31-1），在衬底（21）上的半导体（22）和半导体（22）上的钝化层（25） 并且使用第一掩模（32）局部蚀刻钝化层（25）以暴露半导体（22）的一部分（36），并且不移除形成肖特基接触（42-1）的第一掩模（32） 在所述半导体（22）的暴露部分（36）上的第一材料，然后去除所述第一掩模（32）并使用另外的掩模（44），形成第二材料的步进栅极导体（48-1） 耦合到与肖特基触点（42-1）相邻的钝化层（25）的肖特基接触（42-1）和上覆部分（25-1）。 通过最小化打开钝化层（25）中的肖特基接触窗（35）并在该窗口（35）中形成肖特基接触（42-1）材料之间的工艺步骤，得到的场效应器件（51）的栅极泄漏 -5）具有肖特基门（42-1）。

公开(公告)号：US07119381B2

公开(公告)日：2006-10-10

申请号：US10903784

申请日：2004-07-30

申请人： Matthias Passlack

发明人： Matthias Passlack

IPC分类号： H01L21/00

CPC分类号： H01L29/51 ,  H01L21/823814 ,  H01L27/0605

摘要： A complementary metal-oxide-semiconductor field effect transistor structure includes ion implants in only one of the two complementary devices. The transistor structure generally includes a compound semiconductor substrate and an epitaxial layer structure that includes one or more donor layers that establish a conductivity type for the epitaxial layer structure. The ion implants function to “invert” or “reverse” the conductivity type of the epitaxial layer structure in one of the complementary devices. In the example embodiment, p-type acceptor implants are utilized in the p-channel device, while the n-channel device remains implant-free.

摘要翻译： 互补金属氧化物半导体场效应晶体管结构仅包括两个互补器件中的一个中的离子注入。 晶体管结构通常包括化合物半导体衬底和外延层结构，该外延层结构包括建立外延层结构的导电类型的一个或多个施主层。 离子注入功能在互补器件之一中“反转”或“反转”外延层结构的导电类型。 在示例性实施例中，p型受体植入物用于p沟道器件，而n沟道器件保持无植入。

公开(公告)号：US20060220062A1

公开(公告)日：2006-10-05

申请号：US11100095

申请日：2005-04-05

申请人： Bruce Green ,  Olin Hartin ,  Ellen Lan ,  Philip Li ,  Monte Miller ,  Matthias Passlack ,  Marcus Ray ,  Charles Weitzel

发明人： Bruce Green ,  Olin Hartin ,  Ellen Lan ,  Philip Li ,  Monte Miller ,  Matthias Passlack ,  Marcus Ray ,  Charles Weitzel

IPC分类号： H01L29/739

CPC分类号： H01L29/7785

摘要： In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1-xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1-xAs channel layer (512) is formed over the AlxGa1-xAs layer (506). An AlxGa1-xAs layer (518) is formed over the InxGa1-xAs channel layer (512), and the AlxGa1-xAs layer (518) has a second doped region formed therein. A GaAs layer (520) having a first recess is formed over the AlxGa1-xAs layer (518). A control electrode (526) is formed over the AlxGa1-xAs layer (518). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.

摘要翻译： 在一个实施例中，半导体器件（500）包括形成在衬底（502）上的缓冲层（504）。 在缓冲层（504）之上形成Al x Ga 1-x As层（506），并且在其中形成有第一掺杂区域（508）。 在Al x Ga 1-x 上形成一个In 1 / x Ga 1-x As As沟道层（512） >作为层（506）。 在In 1 x 1 Ga 1-x N上形成Al x Ga 1-x As层（518） 作为沟道层（512）和Al x Ga 1-x As层（518）具有形成在其中的第二掺杂区域。 具有第一凹陷的GaAs层（520）形成在Al 1 Ga 1-x As层（518）上。 控制电极（526）形成在Al 1 Ga 1-x As As层（518）上。 在未掺杂的GaAs层（520）上和控制电极（526）的相对侧上形成掺杂GaAs层（524），并提供第一和第二电流电极。 当用于放大数字调制信号时，半导体器件（500）在宽的温度范围内保持线性操作。