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    Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions
    42.
    发明授权
    Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions 失效
    制造具有精确定义的单晶源极/漏极延伸的SOI器件的方法

    公开(公告)号：US06743689B1

    公开(公告)日：2004-06-01

    申请号：US10341427

    申请日：2003-01-14

    申请人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

    发明人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

    IPC分类号： H01L21336

    CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/458 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

    摘要： Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.

    摘要翻译： 包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造 源/漏扩展的结晶和激活。 实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层 漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分 。

    Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges
    43.
    发明授权
    Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges 失效
    宽颈浅沟槽隔离区，以防止浅沟槽隔离区边缘的应变松弛

    公开(公告)号：US06696348B1

    公开(公告)日：2004-02-24

    申请号：US10314326

    申请日：2002-12-09

    申请人： Qi Xiang

    发明人： Qi Xiang

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232

    摘要： The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isolation technology without relaxation of the portion of the strained silicon layer adjacent to a shallow trench isolation region by laterally extending a shallow trench isolation into the strained silicon layer overlying a silicon germanium layer.

    摘要翻译： 本发明能够制造改进的高速半导体器件。 本发明提供了由应变硅技术提供的更高速度，以及由浅沟槽隔离技术提供的较小的整体器件尺寸，而不会通过将浅沟槽隔离横向延伸到浅沟槽隔离部分而使弛豫与浅沟槽隔离区域相邻的应变硅层的部分松弛 覆盖硅锗层的应变硅层。

    Metal silicide gate transistors
    46.
    发明授权
    Metal silicide gate transistors 有权
    金属硅化物晶体管

    公开(公告)号：US06602781B1

    公开(公告)日：2003-08-05

    申请号：US09734207

    申请日：2000-12-12

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L2144

    CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

    摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

    摘要翻译： 实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了金属在凹部中的部分之外，除去金属。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

    Method for shallow trench isolation using passivation material for trench bottom liner
    47.
    发明授权
    Method for shallow trench isolation using passivation material for trench bottom liner 有权
    浅沟槽隔离方法，使用沟槽底衬的钝化材料

    公开(公告)号：US06524929B1

    公开(公告)日：2003-02-25

    申请号：US09794894

    申请日：2001-02-26

    申请人： Qi Xiang ,  Philip A. Fisher

    发明人： Qi Xiang ,  Philip A. Fisher

    IPC分类号： H01L2176

    CPC分类号： H01L21/76264 ,  H01L21/76283

    摘要： A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate; forming an isolation trench through the silicon active layer, the isolation trench defining at least one active island in the silicon active layer; depositing a passivating insulator in a lower portion of the isolation trench; and filling the isolation trench above the passivating insulator with a trench isolation material.

    摘要翻译： 一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：提供具有硅有源层，介电绝缘层和硅衬底的绝缘体上硅半导体晶片; 通过所述硅有源层形成隔离沟槽，所述隔离沟槽限定所述硅有源层中的至少一个有源岛; 在隔离沟槽的下部沉积钝化绝缘体; 以及用沟槽隔离材料填充钝化绝缘体上方的隔离沟槽。

    Silicide gate transistors
    48.
    发明授权
    Silicide gate transistors 有权
    硅化物栅极晶体管

    公开(公告)号：US06465309B1

    公开(公告)日：2002-10-15

    申请号：US09734185

    申请日：2000-12-12

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L21336

    CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

    摘要： A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.

    摘要翻译： 半导体结构及其制造方法提供由氧氮化物形成的栅极电介质或形成在凹部内的氮化物/氧化物堆叠。 非晶硅沉积在凹槽内的栅极电介质上，金属沉积在非晶硅上。 退火工艺在栅极电介质的凹槽内形成金属硅化物栅极。 可以选择更宽范围的金属材料，因为由氮氧化物或氮化物/氧化物堆叠形成的栅极电介质在硅化过程中保持稳定。 金属硅化物栅极显着降低了栅极和栅极端子之间的薄层电阻。

    Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process
    49.
    发明授权
    Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process 失效
    具有CVD非晶硅层的金属栅极和用于CMOS器件的硅化物和用替代栅极工艺制造的方法

    公开(公告)号：US06440868B1

    公开(公告)日：2002-08-27

    申请号：US09691259

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L21302

    CPC分类号： H01L21/28052 ,  H01L29/517 ,  H01L29/66545 ,  Y10S438/926

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后将金属沉积在CVD非晶硅层上。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

    Reduction of metal silicide/silicon interface roughness by dopant implantation processing
    50.
    发明授权
    Reduction of metal silicide/silicon interface roughness by dopant implantation processing 有权
    通过掺杂剂注入处理减少金属硅化物/硅界面粗糙度

    公开(公告)号：US06376343B1

    公开(公告)日：2002-04-23

    申请号：US09812695

    申请日：2001-03-21

    申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

    发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

    IPC分类号： H01L21425

    CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/665

    摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.

    摘要翻译： 避免了由于特定掺杂剂和金属硅化物的不良相容性而形成浅晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度，或至少大大降低 通过植入与金属硅化物具有相对良好的相容性的第一（主要）掺杂剂物质，使得其最大浓度在高于发生硅化反应的深度的深度处，并且注入具有相对较差相容性的第二（辅助）掺杂剂种类 金属硅化物，其中其最大浓度小于第一（主要）掺杂剂的最大浓度，并且处于低于发生硅化反应的深度的深度。 本发明特别适用于在掺杂Si的衬底上形成NiSi层。