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    Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes
    1.
    发明授权
    Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes 有权
    利用不同组合的金属基嵌入栅电极的半导体器件

    公开(公告)号：US06583012B1

    公开(公告)日：2003-06-24

    申请号：US09781436

    申请日：2001-02-13

    申请人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

    发明人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

    IPC分类号： H01L218234

    CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/28518 ,  H01L21/823842

    摘要： MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of which openings gate insulator layer segments of MOS transistor precursor regions formed in a semiconductor substrate are exposed; selectively forming at least one masking layer segment on the first blanket layer overlying selected ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or silicon over the thus-formed structure, and effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying other ones of the MOS transistor precursor regions. Unnecessary layers remaining after alloying or silicidation reaction are then removed by performing planarization processing, e.g., by CMP. The invention also includes MOS and CMOS devices comprising differently composed in-laid, metal-based gate electrodes.

    摘要翻译： 包括多个晶体管的MOS晶体管和CMOS器件包括具有不同组成的嵌入式金属基栅极的多个晶体管，其特征在于，包括：在绝缘层的底部沉积第一金属填充开口的第一覆盖层， 形成在半导体衬底中的MOS晶体管前体区的开口栅极绝缘体层段露出; 选择性地形成覆盖所选择的MOS晶体管前体区域的第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或硅的第二覆盖层，并且在覆盖其它MOS晶体管前体区域的第一和第二覆盖层的接触部分之间进行合金化或硅化反应。 然后通过进行平坦化处理，例如通过CMP除去在合金化或硅化反应之后残留的不必要的层。 本发明还包括包括不同组合的嵌入式金属基栅极的MOS和CMOS器件。

    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process
    5.
    发明授权
    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process 有权
    具有用于CMOS器件的注入掺杂剂的PVD非晶硅层的金属栅极和用替代栅极工艺制造的方法

    公开(公告)号：US06589866B1

    公开(公告)日：2003-07-08

    申请号：US09691226

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2144

    CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L29/4933

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。 然后在PVD非晶硅层上形成金属。 另外的掺杂剂被注入到PVD非晶硅层中。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同，而PVD非晶硅层的附加掺杂降低了栅电极的电阻率。

    Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process
    6.
    发明授权
    Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process 失效
    具有CVD非晶硅层的金属栅极和用于CMOS器件的阻挡层以及用替代栅极工艺制造的方法

    公开(公告)号：US06436840B1

    公开(公告)日：2002-08-20

    申请号：US09691188

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

    发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

    IPC分类号： H01L21302

    CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/3146 ,  H01L29/4941 ,  H01L29/517 ,  Y10S438/926

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后在CVD非晶硅层上沉积阻挡层。 然后在屏障上形成金属。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 由于防止CVD非晶硅层与金属之间的相互作用的屏障，因此在随后的高温处理期间，阻挡层保留功函数，否则可能形成硅化物并改变功函数。

    Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process
    7.
    发明授权
    Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process 有权
    具有PVD非晶硅层的金属栅极和用于CMOS器件的阻挡层以及用替代栅极工艺制造的方法

    公开(公告)号：US06642590B1

    公开(公告)日：2003-11-04

    申请号：US09691227

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2976

    CPC分类号： H01L29/4941 ,  H01L21/2807

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. A barrier layer is deposited on the PVD amorphous silicon layer. The metal is then formed on the barrier layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer. The barrier layer prevents interaction between the PVD amorphous silicon layer and the metal, thereby allowing higher temperature subsequent processing while preserving the work function of the gate.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。 阻挡层沉积在PVD非晶硅层上。 然后在阻挡层上形成金属。 由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 阻挡层防止PVD非晶硅层和金属之间的相互作用，从而允许更高温度的后续处理，同时保持栅极的功函数。

    Method of forming semiconductor devices with differently composed metal-based gate electrodes
    9.
    发明授权
    Method of forming semiconductor devices with differently composed metal-based gate electrodes 有权
    用不同组合的金属基栅极形成半导体器件的方法

    公开(公告)号：US06518154B1

    公开(公告)日：2003-02-11

    申请号：US09813310

    申请日：2001-03-21

    申请人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

    发明人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

    IPC分类号： H01L213205

    CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975

    摘要： MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g., a MOS transistor) precursor regions of a semiconductor substrate; selectively forming at least one masking layer segment on the first blanket layer overlying selective ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or semi-metal, or silicon, over the thus-formed structure; effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying the other ones of the transistor precursor regions; exposing and selectively removing the masking layer segment; and simultaneously patterning the alloyed and unalloyed/unsilicided portions of the first blanket layer to form metal-based gate electrodes of different composition. The invention also includes MOS and CMOS devices comprising differently composed metal-based gate electrodes.

    摘要翻译： 包括多个晶体管的MOS晶体管和CMOS器件包括不同组成的金属基栅极，其方法包括：在第一和第二有源器件上延伸的薄栅极绝缘层上沉积第一金属的第一覆盖层（例如， ，MOS晶体管）前驱体区域; 选择性地形成覆盖所述MOS晶体管前体区域中的选择性掩模层的所述第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或半金属或硅的第二覆盖层; 在覆盖晶体管前体区域中的另一层的第一和第二覆盖层的接触部分之间发生合金化或硅化反应; 曝光和选择性地去除掩模层段; 并且同时对第一覆盖层的合金化和非合金化/未硅化部分进行构图，以形成不同组成的金属基栅电极。 本发明还包括包含不同组合的金属基栅极的MOS和CMOS器件。

    Silicide gate transistors
    10.
    发明授权
    Silicide gate transistors 有权
    硅化物栅极晶体管

    公开(公告)号：US06368950B1

    公开(公告)日：2002-04-09

    申请号：US09734186

    申请日：2000-12-12

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L213205

    CPC分类号： H01L29/66545 ,  H01L21/28097

    摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

    摘要翻译： 实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了凹部中硅的部分之外，除去硅。 通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。