公开(公告)号：US20240055429A1

公开(公告)日：2024-02-15

申请号：US17818933

申请日：2022-08-10

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/76 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/7606 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02568 ,  H01L21/8256 ,  H01L29/66969 ,  H03K19/20

Abstract: Disclosed is a complementary field effect transistor (CFET) formed from stacked 2D-material transistors. The 2D-material transistors are formed from transition metal dichalcogenide (TMD), which are atomically thin semiconductors. The stacked TMD transistors allow for enhanced drive current and lower switching capacitance, both of which are desirable.

公开(公告)号：US20230008615A1

公开(公告)日：2023-01-12

申请号：US17369532

申请日：2021-07-07

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Junjing BAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/24 ,  H01L27/092 ,  H01L29/66

Abstract: Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

公开(公告)号：US20220173039A1

公开(公告)日：2022-06-02

申请号：US17107078

申请日：2020-11-30

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Haining YANG ,  Xia LI

IPC: H01L23/528 ,  H01L23/50 ,  H01L27/092 ,  H01L27/118

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a buried power rail (BPR) having decreased resistance and a method of fabricating such a semiconductor device with a BPR. An example semiconductor device generally includes a substrate, a first transistor structure disposed above the substrate, a second transistor structure disposed above the substrate, and a BPR structure disposed between the first transistor structure and the second transistor structure. The BPR structure generally includes at least two distinguishable portions, which may be a first portion disposed above a second portion, the second portion having a greater width than the first portion.

公开(公告)号：US20210305250A1

公开(公告)日：2021-09-30

申请号：US16828487

申请日：2020-03-24

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Xia LI ,  Bin YANG

IPC: H01L27/092 ,  H01L29/40 ,  H01L21/8238

Abstract: An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate.

公开(公告)号：US20210273409A1

公开(公告)日：2021-09-02

申请号：US16803668

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/343

Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.

公开(公告)号：US20210240447A1

公开(公告)日：2021-08-05

申请号：US16778749

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Zhongze WANG ,  Periannan CHIDAMBARAM

IPC: G06F7/68 ,  G06F7/533

Abstract: Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals.

公开(公告)号：US20210133549A1

公开(公告)日：2021-05-06

申请号：US16669855

申请日：2019-10-31

Applicant: QUALCOMM Incorporated

Inventor： Zhongze WANG ,  Xia LI ,  Xiaochun ZHU

IPC: G06N3/063 ,  G11C11/412 ,  G11C11/419

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.

公开(公告)号：US20210020790A1

公开(公告)日：2021-01-21

申请号：US16511093

申请日：2019-07-15

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Xia LI ,  Bin YANG

IPC: H01L29/93 ,  H01L29/778 ,  H01L29/66

Abstract: Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

公开(公告)号：US20200312786A1

公开(公告)日：2020-10-01

申请号：US16362951

申请日：2019-03-25

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Kai LIU ,  Xia LI

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/498

Abstract: Certain aspects of the present disclosure provide apparatus for thermal matching of integrated circuits (ICs). One example apparatus generally includes a first substrate, a first IC disposed on the first substrate and having a second substrate, and a second IC disposed on the first substrate. The second IC may include a third substrate, a thermal conductivity adjustment region comprising different material than the third substrate, the thermal conductivity adjustment region being adjacent to a first side of the third substrate, and one or more electrical components formed in one or more layers of the second IC adjacent to a second side of the third substrate, wherein the first side and the second side are opposite sides of the third substrate, and wherein a thermal conductivity of the thermal conductivity adjustment region is closer to a thermal conductivity of the second substrate than a thermal conductivity of the third substrate.

公开(公告)号：US20200098409A1

公开(公告)日：2020-03-26

申请号：US16404549

申请日：2019-05-06

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jianguo YAO

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: A magnetic random access memory (MRAM) array is described. The MRAM array includes bit cells, and each bit cell includes a magnetic tunnel junction (MTJ). The MTJ include a barrier layer between a free layer and a pinned layer. In addition the bit cells are shorted together. The MRAM array also includes wordline (WL) devices, each coupled to one of the bit cells. The MRAM array further includes a tristate bit line (BL) driver coupled to each of the bit cells. The MRAM array also includes a tristate source line (SL) driver coupled to each of the bit cells via the WL devices.