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    Semiconductor package structure having an annular frame with truncated corners
    45.
    发明授权
    Semiconductor package structure having an annular frame with truncated corners 有权

    公开(公告)号：US11171113B2

    公开(公告)日：2021-11-09

    申请号：US16563919

    申请日：2019-09-08

    申请人： MEDIATEK INC.

    发明人： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

    IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

    摘要： A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame.

    Semiconductor package assembly and method for forming the same
    47.
    发明授权
    Semiconductor package assembly and method for forming the same 有权

    公开(公告)号：US10903198B2

    公开(公告)日：2021-01-26

    申请号：US16674298

    申请日：2019-11-05

    申请人： MEDIATEK INC.

    发明人： Chia-Cheng Chang ,  I-Hsuan Peng ,  Tzu-Hung Lin

    IPC分类号： H01L25/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

    摘要： A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

    Stacked fan-out package structure
    48.
    发明授权
    Stacked fan-out package structure 有权

    公开(公告)号：US10692789B2

    公开(公告)日：2020-06-23

    申请号：US15968449

    申请日：2018-05-01

    申请人： MediaTek Inc.

    发明人： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

    IPC分类号： H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

    摘要： A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

    Semiconductor package assembly
    50.
    发明授权
    Semiconductor package assembly 有权

    公开(公告)号：US10177125B2

    公开(公告)日：2019-01-08

    申请号：US15618210

    申请日：2017-06-09

    申请人： MediaTek Inc.

    发明人： Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao

    IPC分类号： H01L25/16 ,  H01L25/10 ,  H01L23/485 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498

    摘要： In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.