公开(公告)号：US20240008242A1

公开(公告)日：2024-01-04

申请号：US17854780

申请日：2022-06-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Carl Radens ,  Albert M. Chu ,  Brent A. Anderson ,  Junli Wang ,  Julien Frougier ,  Ravikumar Ramachandran

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

公开(公告)号：US10832971B2

公开(公告)日：2020-11-10

申请号：US16117258

申请日：2018-08-30

Applicant: International Business Machines Corporation

Inventor： Rajasekhar Venigalla ,  Ravikumar Ramachandran ,  Albert Chu ,  Alan Thomas ,  Kafai Lai

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/308

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.

公开(公告)号：US10693005B2

公开(公告)日：2020-06-23

申请号：US16399181

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Albert M. Chu ,  Eric Eastman ,  Myung-Hee Na ,  Ravikumar Ramachandran

IPC: H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165

Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.

公开(公告)号：US10573646B2

公开(公告)日：2020-02-25

申请号：US16038488

申请日：2018-07-18

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Dechao Guo ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

IPC: H01L21/336 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L21/306 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.

公开(公告)号：US10424574B2

公开(公告)日：2019-09-24

申请号：US15412608

申请日：2017-01-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Albert M. Chu ,  Myung-Hee Na ,  Ravikumar Ramachandran

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.

公开(公告)号：US20190259869A1

公开(公告)日：2019-08-22

申请号：US16399181

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Albert M. Chu ,  Eric Eastman ,  Myung-Hee Na ,  Ravikumar Ramachandran

IPC: H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.

公开(公告)号：US20190097016A1

公开(公告)日：2019-03-28

申请号：US15716705

申请日：2017-09-27

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Albert M. Chu ,  Eric Eastman ,  Myung-Hee Na ,  Ravikumar Ramachandran

IPC: H01L29/49 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/105

CPC classification number: H01L29/785 ,  H01L21/28518 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845 ,  H01L2029/7858

Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.

公开(公告)号：US10242980B2

公开(公告)日：2019-03-26

申请号：US15331351

申请日：2016-10-21

Applicant: International Business Machines Corporation

Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Huiling Shang ,  Reinaldo A. Vega

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10

Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

公开(公告)号：US20180323194A1

公开(公告)日：2018-11-08

申请号：US16038600

申请日：2018-07-18

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Dechao Guo ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.

公开(公告)号：US20180226299A1

公开(公告)日：2018-08-09

申请号：US15804228

申请日：2017-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew M. Greene ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L23/535

CPC classification number: H01L21/823481 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: A dual layer shallow isolation trench region for semiconductor structures including field effect transistors (FETs) and methods for making the same. The first layer of the shallow trench isolation region includes a dielectric material disposed between adjacent FETs. The second layer is an etch resistant material disposed on the dielectric material and has an increased etch resistance relative to the dielectric material. The etch resistant material overlays the shallow trench region to provide the dual layer shallow trench isolation region, which permits self-alignment of contacts to the source and/or drain of FETs.