公开(公告)号：US20050146034A1

公开(公告)日：2005-07-07

申请号：US10748106

申请日：2003-12-24

Applicant: Tatyana Andreyushchenko ,  Kenneth Cadien ,  Paul Fischer ,  Valery Dubin

Inventor： Tatyana Andreyushchenko ,  Kenneth Cadien ,  Paul Fischer ,  Valery Dubin

IPC: H01L21/288 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76843 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76888

Abstract: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.

Abstract translation: 一种方法包括在包括至少一个接触开口的基板表面上形成阻挡层; 在所述接触开口中形成互连; 并降低阻挡层的导电性。 一种方法，包括在包括电介质层和接触开口的衬底表面上形成阻挡层，在接触开口中沉积导电材料，去除足以暴露衬底表面上的阻挡层的导电材料，以及降低导电材料的导电性 阻挡层。 一种包括电路基板的设备，包括至少一个有源层，包括至少一个接触点，至少一个有源层上的电介质层，介电层表面上的阻挡层，阻挡层的一部分已经被转变 从第一电导率到第二不同和降低的电导率，以及耦合到所述至少一个接触点的互连。

公开(公告)号：US20050136654A1

公开(公告)日：2005-06-23

申请号：US10744119

申请日：2003-12-22

Applicant: Chin-Chang Cheng ,  Valery Dubin

Inventor： Chin-Chang Cheng ,  Valery Dubin

IPC: B32B15/00 ,  B32B15/04 ,  C23C18/16 ,  C23C18/34 ,  C23C18/36 ,  H01L21/288 ,  H01L21/44 ,  H01L21/768 ,  H05K3/24

CPC classification number: H01L21/76846 ,  C23C18/1651 ,  C23C18/34 ,  C23C18/36 ,  H01L21/288 ,  H01L21/76838 ,  H01L21/76849 ,  H05K3/244 ,  H05K2203/072 ,  H05K2203/1476 ,  Y10T428/12576 ,  Y10T428/12861

Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.

公开(公告)号：US20050112856A1

公开(公告)日：2005-05-26

申请号：US10981207

申请日：2004-11-03

Applicant: Valery Dubin ,  Christopher Thomas ,  Vinay Chikarmane

Inventor： Valery Dubin ,  Christopher Thomas ,  Vinay Chikarmane

IPC: B32B9/00 ,  C25D5/34 ,  H01L21/02 ,  H01L21/20 ,  H01L21/288 ,  H01L21/768

CPC classification number: H01L21/02068 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76873 ,  Y10T428/24926

Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.

Abstract translation: 种子层处理以除去种子层中可能导致在互连电路特征中形成空隙的杂质。 在一个实施方案中，种子层在还原环境中被加热。 在另一个实施方案中，种子层用表面活性剂洗涤，该表面活性剂与在种子层上形成电路特征的其余部分时所用的表面活性剂相容。 又一实施例结合了两种技术。

公开(公告)号：US06271591B1

公开(公告)日：2001-08-07

申请号：US09312937

申请日：1999-05-17

Applicant: Valery Dubin ,  Chiu Ting

Inventor： Valery Dubin ,  Chiu Ting

IPC: H01L2348

CPC classification number: H01L23/53233 ,  H01L21/288 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating copper-aluminum metallization utilizing the technique of electroless copper deposition is described. The method provides a self-encapsulated copper-aluminum metallization structure.

Abstract translation: 描述了利用无电铜沉积技术制造铜 - 铝金属化的方法。 该方法提供了一种自封装的铜 - 铝金属化结构。

公开(公告)号：US5969422A

公开(公告)日：1999-10-19

申请号：US857129

申请日：1997-05-15

Applicant: Chiu Ting ,  Valery Dubin

Inventor： Chiu Ting ,  Valery Dubin

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/45

CPC classification number: H01L21/76874 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002

Abstract: A high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal, such as Cu, and a refractory metal, such as Ta. The seed layer also functions as a barrier/adhesion layer for the subsequently plated Cu or Cu-base alloy. Another embodiment comprises initially depositing a refractory metal barrier layer before depositing the seed layer.

Abstract translation: 通过在包含催化活性金属如Cu的合金和诸如Ta的难熔金属的种子层上电镀或化学镀Cu或Cu基合金来形成高导电性互连结构。 种子层还用作随后镀覆的Cu或Cu基合金的阻挡/粘合层。 另一个实施方案包括在沉积种子层之前首先沉积难熔金属阻挡层。

公开(公告)号：US20150206861A1

公开(公告)日：2015-07-23

申请号：US14593993

申请日：2015-01-09

Applicant: Valery Dubin

Inventor： Valery Dubin

IPC: H01L25/16 ,  H01L33/48 ,  H01L33/52 ,  H01L21/677 ,  H01L21/48 ,  H01L21/78 ,  H01L21/67 ,  H01L33/40 ,  H01L33/62

CPC classification number: H01L25/167 ,  H01L21/486 ,  H01L21/67161 ,  H01L21/67236 ,  H01L21/67703 ,  H01L21/78 ,  H01L25/165 ,  H01L33/40 ,  H01L33/486 ,  H01L33/52 ,  H01L33/56 ,  H01L33/62 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2933/0016 ,  H01L2933/0033 ,  H01L2933/005 ,  H01L2933/0066 ,  Y10T29/53174 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Light emitting diode (LED) package structures employing large area substrates are described. Panel or reel-to-reel substrate processing is utilized in the manufacture of such LED package structures. In some embodiments, electrochemically deposited metal patterns and through substrate vias (TSuVs) are formed through glass substrates and/or interposers. In some embodiments, the metal deposited into the TSuVs offer high thermal conductivity a low coefficient of thermal expansion (CTE) that is to closely match the CTE of the glass. Singulated LED package structures including a plurality of LEDs arrayed for displays, such as, but not limited to, liquid crystal displays (LCDs) and LED displays or for general purpose LED light sources are described, as are LED package structures including active devices (e.g., ICs) and/or passive devices (e.g., capacitors, inductors, resistors, etc.) integrated with LEDs at the package level.

Abstract translation: 描述了采用大面积衬底的发光二极管（LED）封装结构。 面板或卷对盘基板处理用于制造这种LED封装结构。 在一些实施例中，电化学沉积的金属图案和通过衬底通孔（TSuV）通过玻璃衬底和/或插入件形成。 在一些实施例中，沉积到TSuV中的金属提供高导热率，其与玻璃的CTE密切匹配的低热膨胀系数（CTE）。 描述了包括阵列用于显示器（例如但不限于液晶显示器（LCD））和LED显示器或用于通用LED光源的多个LED的单个LED封装结构，包括有源器件（例如， ，IC）和/或与封装级别的LED集成的无源器件（例如，电容器，电感器，电阻器等）。

公开(公告)号：US20080241575A1

公开(公告)日：2008-10-02

申请号：US11692330

申请日：2007-03-28

Applicant: Adrein R. Lavoie ,  Valery Dubin ,  John Plombon ,  Kari Harkonen ,  Arnel M. Fajardo

Inventor： Adrein R. Lavoie ,  Valery Dubin ,  John Plombon ,  Kari Harkonen ,  Arnel M. Fajardo

IPC: H01L29/12 ,  H01L21/311

CPC classification number: H01L21/76849 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76883 ,  H01L21/76897 ,  H01L29/78 ,  Y10T428/12528

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include heating a substrate comprising a patterned metallic region to about 145 C or below in a reaction space, introducing an aluminum co-reactant into the reaction space, wherein an aluminum material is formed on the patterned metallic region, but not on non-metallic regions.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括在反应空间中将包含图案化金属区域的基底加热至约145℃或更低，将铝共反应物引入反应空间，其中铝材料形成在图案化的金属区域上， 金属区域。

公开(公告)号：US20080003801A1

公开(公告)日：2008-01-03

申请号：US11897792

申请日：2007-08-30

Applicant: Valery Dubin ,  Thomas Dory

Inventor： Valery Dubin ,  Thomas Dory

IPC: H01L21/44

CPC classification number: H01L23/373 ,  B82Y10/00 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01037 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  Y10S977/732 ,  Y10S977/744 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T428/30

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract translation: 根据本发明的一个方面，提供一种构造电子组件的方法。 在其上集成形成的半导体晶片的背面上形成金属层。 然后，在金属层上形成多孔层。 在孔的底部的多孔层的阻挡层变薄。 然后，催化剂沉积在孔的底部。 然后在孔中生长碳纳米管。 然后在多孔层和碳纳米管上形成另一层金属。 然后将半导体晶片分离成微电子管芯。 将模具结合到半导体衬底，将散热器放置在管芯的顶部，并且由这种组装产生的半导体封装被密封。 在散热器的顶部形成热界面。 然后将散热器放置在热界面的顶部。

公开(公告)号：US20070292855A1

公开(公告)日：2007-12-20

申请号：US11207000

申请日：2005-08-19

Applicant: Valery Dubin ,  Florian Gstrein ,  Jonathan Lueker

Inventor： Valery Dubin ,  Florian Gstrein ,  Jonathan Lueker

IPC: C12Q1/68 ,  C12M3/00

CPC classification number: C12Q1/6816 ,  C12Q2565/607

Abstract: A device having a functionalized electrode having a probe molecule, wherein the device has an ability to electrically detect a molecular binding event between the probe molecule and a target molecule by a polarization change of the functionalized electrode is disclosed. The device could also include an unfunctionalized electrode that does not have the probe molecule and the device could have an ability to electrically detect the molecular binding event between the probe molecule and the target molecule by a polarization change between the functionalized electrode and the unfuctionalized electrode.

Abstract translation: 具有具有探针分子的官能化电极的器件，其中该器件具有通过官能化电极的偏振变化电探测探针分子与靶分子之间的分子结合事件的能力。 该装置还可以包括不具有探针分子的未官能化电极，并且该装置可以具有通过功能化电极和未通电电极之间的偏振变化来电探测分子与靶分子之间的分子结合事件的能力。

公开(公告)号：US20070284744A1

公开(公告)日：2007-12-13

申请号：US11893869

申请日：2007-08-15

Applicant: Valery Dubin ,  Peter Moon

Inventor： Valery Dubin ,  Peter Moon

IPC: H01L23/528

CPC classification number: H01L21/76843 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.

Abstract translation: 在一个实施例中，一种装置包括具有在层间电介质（ILD）中形成的至少一个互连的第一层，在第一层上形成的具有第二至少一个互连的第二层，在第二层上形成的第三层， 第三层限定第二至少一个互连和第三层之间的至少一个空气间隙，以及至少一个分流器，其选择性地覆盖第一和第二至少一个互连。 在另一个实施例中，一种方法包括形成包括ILD和第一至少一个互连的第一层，在第一层上形成第二层，第二层具有第二至少一个互连，在第一层上沉积至少一个分流 以及第二至少一个互连，在所述第二层上形成第三层，以及蒸发所述第二层的一部分以在所述第二至少一个互连和所述第三层之间产生至少一个空气间隙。