公开(公告)号：US20070269931A1

公开(公告)日：2007-11-22

申请号：US11752219

申请日：2007-05-22

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L21/00

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

公开(公告)号：US20050127508A1

公开(公告)日：2005-06-16

申请号：US10897124

申请日：2004-07-23

Applicant: In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

Inventor： In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/44 ,  H01L29/40

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

Abstract translation: 焊料凸块结构可以具有形成在半导体芯片的芯片焊盘上的金属螺柱。 金属螺柱的表面可以镀有焊料。 金属螺柱可以位于衬底的衬底焊盘上。 衬底垫可以具有施加到其上的预焊料。 在焊料回流之后，焊料凸点可以具有凹形。

公开(公告)号：US06504450B2

公开(公告)日：2003-01-07

申请号：US09798908

申请日：2001-03-06

Applicant: Duk-Yong Kim ,  Yoon-Bae Lee ,  Gyu-Sang Hwang ,  In-Young Lee ,  Sang-Wook Bang ,  Chang-Yun Seo ,  Kyoung-Ho Lee ,  Sung-Soo Lee ,  Yoon-Yong Kim ,  Taek-Dong Kim

Inventor： Duk-Yong Kim ,  Yoon-Bae Lee ,  Gyu-Sang Hwang ,  In-Young Lee ,  Sang-Wook Bang ,  Chang-Yun Seo ,  Kyoung-Ho Lee ,  Sung-Soo Lee ,  Yoon-Yong Kim ,  Taek-Dong Kim

IPC: H01P118

CPC classification number: H01P1/184

Abstract: A signal process apparatus of the present invention is capable of shifting phases of signals inputted thereto and attenuating the signals, simultaneously. The signal process apparatus includes a dielectric member provided with a first and a second portions, a plurality of transmission lines positioned opposite the dielectric member for transmitting the signals and means for rotating the dielectric member to an axis perpendicular to a surface of the dielectric member which is parallel to the transmission lines. In the signal process apparatus, a dielectric constant of the first portion is different from that of the second portion. Each of the signals is inputted to a corresponding transmission line. After each of the signals is passing through the corresponding transmission line, it has a phase shifted by rotating the dielectric member.

公开(公告)号：US06292300B1

公开(公告)日：2001-09-18

申请号：US09562888

申请日：2000-05-01

Applicant: Sukhan Lee ,  Jideog Kim ,  In Young Lee

Inventor： Sukhan Lee ,  Jideog Kim ,  In Young Lee

IPC: G02B2710

CPC classification number: G11C13/042 ,  G02B26/0833 ,  G02B26/101 ,  G11B7/0065 ,  G11B7/08564 ,  G11C13/04

Abstract: An apparatus for generating a coherent beam array from a single light source using independently switchable 45-degree mirrors. In the independent coherent beam array generating apparatus, multiple coherent beams can be generated from a single light source by selectively rotating micro mirrors of two mirror arrays.

Abstract translation: 一种用于使用独立可切换的45度反射镜从单个光源产生相干光束阵列的装置。 在独立相干光束阵列发生装置中，可以通过选择性地旋转两个反射镜阵列的微镜从单个光源产生多个相干光束。

公开(公告)号：US20170162544A1

公开(公告)日：2017-06-08

申请号：US15331801

申请日：2016-10-21

Applicant: Byoung Soo KWAK ,  Tae Hong MIN ,  In Young LEE ,  Tae Je CHO

Inventor： Byoung Soo KWAK ,  Tae Hong MIN ,  In Young LEE ,  Tae Je CHO

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/1403

Abstract: There is provided a semiconductor device, enhanced with process capability and reliability by way of flow control of an adhesive material to fix semiconductor chips. The semiconductor device includes a first semiconductor chip including a first surface and a second surface opposite to each other, a flow regulating structure formed at the first surface of the first semiconductor chip, and a second semiconductor chip mounted on the first surface of the first semiconductor chip. The second semiconductor chip overlaps at least a portion of the flow regulating structure.

公开(公告)号：US08941245B2

公开(公告)日：2015-01-27

申请号：US13533473

申请日：2012-06-26

Applicant: Chang-Cheol Lee ,  Hyun-Jun Kim ,  In-Young Lee ,  Ki-Kwon Jeong

Inventor： Chang-Cheol Lee ,  Hyun-Jun Kim ,  In-Young Lee ,  Ki-Kwon Jeong

IPC: H01L23/52 ,  H01L23/13 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/13 ,  H01L21/565 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1815

Abstract: A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

Abstract translation: 半导体封装包括具有通过其形成的第一开口的衬底，以倒装芯片方式堆叠在衬底上并具有穿过其中的第二开口的第一半导体芯片，以倒装芯片方式堆叠在第一半导体芯片上的第二半导体芯片，以及 具有通过其形成的第三开口，以及覆盖所述第一半导体芯片和所述第二半导体芯片并填充所述基板和所述第一半导体芯片之间的空间的模塑材料，所述第一半导体芯片和所述第二半导体芯片之间的空间，以及填充 第一开口，第二开口和第三开口中的每一个。

公开(公告)号：US20110147946A1

公开(公告)日：2011-06-23

申请号：US13027594

申请日：2011-02-15

Applicant: In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

Inventor： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract translation: 一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。 在集成电路区域上形成第一金属层图案。 通孔形成为延伸穿过第一金属层图案和集成电路区域。 最终的金属层图案形成在第一金属层图案之上并且在通孔内。 在通孔内形成插头。 此后，形成钝化层以覆盖最终金属层图案。

公开(公告)号：US20110001580A9

公开(公告)日：2011-01-06

申请号：US12006996

申请日：2008-01-08

Applicant: Duk-Yong Kim ,  Kyoung-Ho Lee ,  In-Young Lee

Inventor： Duk-Yong Kim ,  Kyoung-Ho Lee ,  In-Young Lee

IPC: H01P1/18

CPC classification number: H01P1/184

Abstract: A variable phase shifter is provided. In the variable phase shifter, a fixed substrate, which is a dielectric substrate, is fixedly mounted in a housing and has at least one arc-shaped microstrip line on one surface thereof. A rotation substrate, which is a dielectric substrate, is rotatably mounted in the housing, in contact with the other surface of the fixed substrate and has a slot line on the contact surface thereof. Microstrip-slot line coupling takes place between the microstrip line and the slot line even during rotation. Both ends of the microstrip line are connected to an output port of the variable phase shifter and the slot line is electrically connected to an input port of the variable phase shifter, for receiving an input signal.

Abstract translation: 提供可变移相器。 在可变移相器中，作为电介质基板的固定基板被固定地安装在壳体中，并且在其一个表面上具有至少一个弧形的微带线。 作为电介质基板的旋转基板可旋转地安装在壳体中，与固定基板的另一表面接触，并且在其接触表面上具有槽线。 即使在旋转期间，微带线耦合也在微带线和槽线之间进行。 微带线的两端连接到可变移相器的输出端口，并且时隙线电连接到可变移相器的输入端口，用于接收输入信号。

公开(公告)号：US20100285635A1

公开(公告)日：2010-11-11

申请号：US12840656

申请日：2010-07-21

Applicant: Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

Inventor： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC: H01L21/60 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20100252935A1

公开(公告)日：2010-10-07

申请号：US12728683

申请日：2010-03-22

Applicant: In Young Lee ,  Donghyeon Jang ,  Namseog Kim

Inventor： In Young Lee ,  Donghyeon Jang ,  Namseog Kim

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L24/73 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13009 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/17051 ,  H01L2224/17505 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: Provided are a semiconductor device and a method for fabricating the same according to an embodiment. In the method, a portion of a substrate comprising a pad is removed to form a via hole. An insulating layer is formed on the substrate. A portion of the insulating layer is removed to form an opening part comprising a plurality of openings exposing portions of the pad. A through electrode is formed to fill the via hole and to be electrically connected to the pad through one of the plurality of openings. A portion of the pad is exposed by another opening among the plurality of openings.

Abstract translation: 提供根据实施例的半导体器件及其制造方法。 在该方法中，去除包括衬垫的衬底的一部分以形成通孔。 在基板上形成绝缘层。 去除绝缘层的一部分以形成包括露出焊盘部分的多个开口的开口部分。 形成贯通电极以填充通孔并且通过多个开口中的一个电连接到焊盘。 垫的一部分由多个开口中的另一个开口暴露。