公开(公告)号：US12156638B2

公开(公告)日：2024-12-03

申请号：US17163834

申请日：2021-02-01

Applicant: OLYMPUS CORPORATION

Inventor： Takeshi Murata

IPC: A61B1/008 ,  A61B1/005 ,  A61B1/01

Abstract: A medical device includes an insertion unit; and a drive unit, the insertion unit has first, second and third lumens, the drive unit has first and second pulleys disposed to be movable advance and retraction, first and second wires are wound on the first and second pulleys, respectively, and a pulling mechanism to pull the first and second pulleys toward a proximal end side, the first wire has a first end inserted into the first lumen and fixed to a distal end side of the insertion unit and a second end inserted into the second lumen and fixed to the distal end side of the insertion unit, and the second wire has a first end inserted into the third lumen and fixed to the distal end side of the insertion unit and a second end fixed to the drive unit.

公开(公告)号：US12154985B2

公开(公告)日：2024-11-26

申请号：US18232640

申请日：2023-08-10

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chen Zhang ,  Julien Frougier ,  Alexander Reznicek ,  Shogo Mochizuki

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

公开(公告)号：USD1052219S1

公开(公告)日：2024-11-19

申请号：US29942579

申请日：2024-05-16

Applicant: Makeblock Co., Ltd.

Designer： Jianjun Wang

公开(公告)号：US12146877B2

公开(公告)日：2024-11-19

申请号：US17082799

申请日：2020-10-28

Applicant: Meso Scale Technologies, LLC.

Inventor： Mark Billadeau ,  Paul Freese ,  Alan Kishbaugh ,  Gisbert Spieles ,  Nicholas Fox-Lyon

IPC: G01N33/543 ,  C12Q1/00 ,  G01N21/66 ,  G01N21/69 ,  G01N21/76

Abstract: The specification provides an assay electrode including a composite containing a matrix and a multiplicity of graphene particles dispersed therein.

公开(公告)号：US12137869B2

公开(公告)日：2024-11-12

申请号：US17200105

申请日：2021-03-12

Applicant: OLYMPUS CORPORATION

Inventor： Hirokazu Godo ,  Yamato Kanda ,  Yukihiro Sugimoto

IPC: A61B1/00 ,  G06T7/11

Abstract: An image processing apparatus includes a processor. The processor is configured to output second and third images corresponding to a continuous first image respectively to first and second routes, analyze the second image and output an analysis result, and generate a fourth image based on the third image and the analysis result and continuously output the fourth image. When acquiring the third image, the processor completes the generation of the fourth image before acquiring an analysis result by the second image generated based on a same first image as the first image, which is a generation source of the third image.

公开(公告)号：US12137189B2

公开(公告)日：2024-11-05

申请号：US18480577

申请日：2023-10-04

Applicant: BROTHER KOGYO KABUSHIKI KAISHA

Inventor： Yutaka Urakawa

IPC: H04N1/00

Abstract: A first controller of an image forming apparatus executes a remote display control. The remote display control is control of, in response to receiving a start request from one of a plurality of information processing apparatuses, transmitting remote screen data to a requesting information processing apparatus. A second controller of the requesting information processing apparatus displays a remote screen in accordance with the remote display control by the first controller. A determination controller determines whether the remote display control is currently executed by a previous request. The first controller is configured to: in response to determining that the remote display control is not currently executed by the previous request, execute the remote display control for the requesting information processing apparatus; and in response to determining that the remote display control is currently executed by the previous request, not execute the remote display control for the requesting information processing apparatus.

公开(公告)号：US12137187B2

公开(公告)日：2024-11-05

申请号：US18484026

申请日：2023-10-10

Applicant: BROTHER KOGYO KABUSHIKI KAISHA

Inventor： Yutaka Urakawa ,  Tomoya Kaneko

IPC: H04N1/00 ,  G06F3/14

Abstract: An image forming apparatus includes a communication interface, a display, and a controller configured to, when the image forming apparatus is remotely connected with an information processing device via the communication interface, transmit, to the information processing device, screen data for causing the information processing device to display a screen corresponding to a display screen being displayed on the display, when receiving remote access from the information processing device, perform display processing for the display screen in accordance with the remote access, and when the remote access is received while a particular screen is being displayed as the display screen on the display, impose a display restriction on the display screen.

公开(公告)号：US12136931B2

公开(公告)日：2024-11-05

申请号：US17983576

申请日：2022-11-09

Applicant: Renesas Electronics Corporation

Inventor： Pratama Fajarmega ,  Tatsuo Nishino ,  Takehiro Shimizu

IPC: H03M1/46 ,  H03M1/06 ,  H03M1/10 ,  H03M1/38 ,  H03M1/76

Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.

公开(公告)号：US12136836B2

公开(公告)日：2024-11-05

申请号：US17479214

申请日：2021-09-20

Applicant: Renesas Electronics America Inc.

Inventor： Sungkeun Lim ,  Yen-Mo Chen ,  Keeho Shin

IPC: H02J7/00 ,  H02J7/34

Abstract: Battery charger systems and apparatuses are described. In an example, an apparatus may include a first controller, a first port connected to the first controller, a first charger module connected to the first controller, a second controller, a second port connected to the second controller, and a second charger module connected to the second controller. The first controller may be configured to form a first connection path between the first charger module and the second port via the second controller. The first controller may be further configured to form a second connection path between the second charger module and the first port via the first controller.

公开(公告)号：US12130749B2

公开(公告)日：2024-10-29

申请号：US18113132

申请日：2023-02-23

Applicant: International Business Machines Corporation

Inventor： Shakti Kapoor ,  Nelson Wu ,  Manoj Dusanapudi

IPC: G06F12/1027 ,  G06F7/58 ,  G06F9/30 ,  G06F12/0882 ,  G06F12/0891 ,  G06F13/16

CPC classification number: G06F12/1027 ,  G06F7/586 ,  G06F9/30043 ,  G06F9/30134 ,  G06F12/0882 ,  G06F12/0891 ,  G06F13/1626 ,  G06F13/1668

Abstract: Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.