知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

43337 records (took 0.042 seconds)

    Safety for wearable virtual reality devices via object detection and tracking
    31.
    发明授权
    Safety for wearable virtual reality devices via object detection and tracking 有权

    公开(公告)号：US12125157B2

    公开(公告)日：2024-10-22

    申请号：US18069455

    申请日：2022-12-21

    Applicant: Ultrahaptics IP Two Limited

    Inventor： David S. Holz ,  Robert Samuel Gordon ,  Matias Perez

    IPC: G06T19/00 ,  G06F3/00 ,  G06F3/01 ,  G06V40/20

    CPC classification number: G06T19/006 ,  G06F3/00 ,  G06F3/011 ,  G06V40/28

    Abstract: The technology disclosed can provide improved safety by detecting potential unsafe conditions (e.g., collisions, loss of situational awareness, etc.) confronting the user of a wearable (or portable) sensor configured to capture motion and/or determining the path of an object based on imaging, acoustic or vibrational waves. Implementations can enable improved safety to users of virtual reality for machine control and/or machine communications applications using wearable (or portable) devices, e.g., head mounted displays (HMDs), wearable goggles, watch computers, smartphones, and so forth, or mobile devices, e.g., autonomous and semi-autonomous robots, factory floor material handling systems, autonomous mass-transit vehicles, automobiles (human or machine driven), and so forth, equipped with suitable sensors and processors employing optical, audio or vibrational detection.

    Scheduling of threads for clusters of processors
    33.
    发明授权
    Scheduling of threads for clusters of processors 有权

    公开(公告)号：US12118384B2

    公开(公告)日：2024-10-15

    申请号：US17452872

    申请日：2021-10-29

    Applicant: BlackBerry Limited

    Inventor： Elad Lahav

    IPC: G06F3/00 ,  G06F9/48

    CPC classification number: G06F9/4881

    Abstract: In some examples, a system includes a plurality of processors and a kernel scheduler. The kernel scheduler associates each respective processor of the plurality of processors with a collection of clusters, wherein each cluster of the collection of clusters represents a respective different subset of the plurality of processors, and the respective processor is a member of each cluster of the collection of clusters. For each corresponding cluster of the collection of clusters, the kernel scheduler maintains a data structure associated with a ready queue of the kernel scheduler, the data structure comprising elements representing thread priorities, wherein an element of the data structure is associated with an ordered list of threads in the ready queue.

    Systems and methods for NVMe over fabric (NVMe-oF) namespace-based zoning
    34.
    发明授权
    Systems and methods for NVMe over fabric (NVMe-oF) namespace-based zoning 有权

    公开(公告)号：US12118231B2

    公开(公告)日：2024-10-15

    申请号：US17386305

    申请日：2021-07-27

    Applicant: DELL PRODUCTS L.P.

    Inventor： Claudio Desanti ,  Joseph LaSalle White ,  Erik Smith

    IPC: G06F3/00 ,  G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/067

    Abstract: A traditional storage platform performs many basic functions, such as storage partitions allocation (i.e., namespace masking) and many advanced functions, such as deduplication or dynamic storage allocation. These functions need to be managed and this results in a multiple management system paradigm in which a fabric management application manages the fabric connectivity policies (i.e., zoning), while a storage management application manages the storage namespace mappings and advanced functions. Embodiments herein provide for centralized management for both connectivity and storage namespace mapping, among other advanced features. Namespace zoning information may comprise namespace zone groups, namespace zones, namespace zone members, namespace zone aliases, and namespace zone alias members, which expand the Non-Volatile Memory Express (NVMe) over Fabrics (NVMe-oF) zoning framework from just connectivity control to full namespace allocation.

    Non-volatile memory integrated with artificial intelligence system for preemptive block management
    38.
    发明授权
    Non-volatile memory integrated with artificial intelligence system for preemptive block management 有权

    公开(公告)号：US12099743B2

    公开(公告)日：2024-09-24

    申请号：US17709745

    申请日：2022-03-31

    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

    Inventor： Liang Li ,  Loc Tu ,  Yinfeng Yu ,  Xuan Tian

    IPC: G06F3/00 ,  G06F3/06 ,  G06N5/04

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06N5/04

    Abstract: A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.

Patent Agency Ranking