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公开(公告)号：US20250068327A1
公开(公告)日：2025-02-27
申请号：US18454253
申请日：2023-08-23
Applicant: Western Digital Technologies, Inc.
Inventor： Liang Li , Xuan Tian , Ming Wang , Jiahui Yuan
IPC: G06F3/06
Abstract: Technology for managing non-volatile memory. A bitmap may be maintained in NAND memory cells. The bits in the bitmap map to an address (e.g., PBA) in the NAND memory cells. Each bit has either a first value to indicate that the corresponding address stores valid data or a second value to indicate that the corresponding address does not store value data. Garbage collection may be performed based on the bitmap. Bit-level memory operations are performed to maintain the bitmap. Bit-level erase may be performed to erase a memory cell to have a value that indicates a valid/invalid status. The bitmap may contain unencoded data. In one aspect, a one's complement to the bitmap is stored in the NAND memory cells. The one's complement has opposite values as the regular bitmap. The system may compare the values in the regular bitmap and the one's complement bitmap for data integrity.
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公开(公告)号：US20240386962A1
公开(公告)日：2024-11-21
申请号：US18229978
申请日：2023-08-03
Applicant: Western Digital Technologies, Inc.
Inventor： Dandan Yi , Xuan Tian , Liang Li , Vincent Yin
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in memory holes. The memory holes are arranged in rows comprising strings which are grouped into blocks comprising a first plane and a second plane. A control means is configured to program memory cells of the first plane and the second plane connected to one of the word lines using iterations of a program operation. The control means terminates programming of the first plane prior to completing programming of the first plane in response to determining the first plane programs slower than the second plane by a predetermined number of the iterations of the program operation. The control means adjusts the predetermined number of the iterations based on an additional verify iteration performed on at least some of the memory cells beyond the iterations of the program operation.
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公开(公告)号：US20240296882A1
公开(公告)日：2024-09-05
申请号：US18224202
申请日：2023-07-20
Applicant: Western Digital Technologies, Inc.
Inventor： Ke Zhang , Liang Li , Jiahui Yuan
IPC: G11C11/4096 , G11C11/4076 , G11C11/408
CPC classification number: G11C11/4096 , G11C11/4076 , G11C11/4085
Abstract: Method for performing a memory operation with respect to a memory structure having “N”-number of planes, each plane comprising “M”-number of blocks and “X”-number of word lines arranged in a serial order, and electrically connected with each plane are: a voltage bias source, an electronic switching component, and row decoder, the method comprising: with respect to each plane, selecting a block and a word line for application of the operation, wherein the operation has not been applied to the selected block and word line, the selected block of one plane is located in a different block group from the selected block of another plane, and the selected word line of one plane is in a different position within the serial order from a position of the selected word line of another plane; and using the voltage bias source, concurrently applying the operation to the selected blocks and selected word lines.
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4.发明授权公开(公告)号：US11978507B2
公开(公告)日：2024-05-07
申请号：US17688999
申请日：2022-03-08
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
CPC classification number: G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3459
Abstract: To remedy short term data retention issues, a non-volatile memory performs a multi-pass programming process to program data into a set of non-volatile memory cells and identifies non-volatile memory cells that experienced downward threshold voltage drift after a first pass of the multi-pass programming process and prior to a final pass of the multi-pass programming process. The final pass of the multi-pass programming process comprises programming non-volatile memory cells not identified to have experienced the downward threshold voltage drift to a set of final target threshold voltages and purposefully overprogramming non-volatile memory cells identified to have experienced the downward threshold voltage drift to threshold voltages greater than respective final target threshold voltages by one or more offsets.
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公开(公告)号：US20230410910A1
公开(公告)日：2023-12-21
申请号：US17752208
申请日：2022-05-24
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
CPC classification number: G11C16/10 , G11C16/0483 , H01L27/11556 , G11C16/24 , G11C16/3459
Abstract: An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.
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Patent Agency Ranking
公开(公告)号：US20230402109A1
公开(公告)日：2023-12-14
申请号：US17837345
申请日：2022-06-10
Applicant: Western Digital Technologies, Inc.
CPC classification number: G11C16/3459 , G11C16/3404 , G11C16/102 , G11C16/26 , G11C16/08
Abstract: Technology is disclosed herein for open block boundary group programming of non-volatile memory such as NAND. The open block boundary group could potentially be read in response to a request from a host for the data stored in the group. In an aspect, the memory system will determine whether programming a group of memory cells in a selected block will result in an open block. If it will not result in an open block, then the memory system uses a first set of programming parameters to program the group. However, if it will result in an open block then the memory system uses a second set of programming parameters to program the boundary group. The programming parameters may include verify levels and/or a program voltage step size. The second set of programming parameters can tighten Vt distributions, which mitigates mis-reads if the boundary group is read.
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公开(公告)号：US11775374B2
公开(公告)日：2023-10-03
申请号：US17231344
申请日：2021-04-15
Applicant: Western Digital Technologies, Inc.
Inventor： Liang Li , Chenxiao Xu , Qin Zhen
CPC classification number: G06F11/079 , G06F11/0727 , G06F11/0754 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3459 , H10B41/27 , H10B43/27
Abstract: Apparatuses and techniques are described for detecting a defect in a memory cell array during program operations. A defect can be detected by comparing the programming speed of memory cells connected to different word lines, for one or more programmed data states. The comparison can involve adjacent word lines in a block, or word lines in different blocks and planes. The comparison involves comparing two word lines in terms of a number of program-verify loops used to reach the programmed data states or to transition between programmed data states. If a program loop delta is not within an allowable range for one or more of the programmed data states, it can be concluded that a defect is present. The block which has the slower programming word line can be identified as a bad block.
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公开(公告)号：US20230091314A1
公开(公告)日：2023-03-23
申请号：US17481575
申请日：2021-09-22
Applicant: Western Digital Technologies, Inc.
Inventor： Ming Wang , Liang Li , Jiahui Yuan
Abstract: A memory system separately programs memory cells connected by a common word line to multiple sets of data states with the set of data states having higher threshold voltage data states being programmed before the set of data states having lower threshold voltage data states. The memory system also separately programs memory cells connected by an adjacent word line to the multiple sets of data states such that memory cells connected by the adjacent word line are programmed to higher data states after memory cells connected by the common word line are programmed to higher data states and prior to memory cells connected by the common word line are programmed to lower data states.
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公开(公告)号：US11557346B2
公开(公告)日：2023-01-17
申请号：US17336314
申请日：2021-06-02
Applicant: Western Digital Technologies, Inc.
IPC: G11C16/04 , G11C16/10 , G11C16/34 , H01L27/11582
Abstract: Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.
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公开(公告)号：US11309041B2
公开(公告)日：2022-04-19
申请号：US16837313
申请日：2020-04-01
Applicant: Western Digital Technologies, Inc.
Abstract: Apparatuses and techniques are described for determining if a block of memory cells is slow-erasing during an erase operation for the block. An erase operation performs an additional verify test in a specified erase-verify iteration to check the position of the upper tail of the threshold voltage distribution of the memory cells of a block. If the upper tail is too high, this indicates a slow-erasing block, even if the erase operation is successfully completed within an allowable number of erase-verify iterations. The additional verify test can be initiated using a prefix command which is transmitted with an erase command to the memory chip. Or, it can be initiated by a device parameter on the memory chip.
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