Invention Publication
- Patent Title: INDEPENDENT PLANE CONCURRENT MEMORY OPERATION IN NON-VOLATILE MEMORY STRUCTURES
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Application No.: US18224202Application Date: 2023-07-20
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Publication No.: US20240296882A1Publication Date: 2024-09-05
- Inventor: Ke Zhang , Liang Li , Jiahui Yuan
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: G11C11/4096
- IPC: G11C11/4096 ; G11C11/4076 ; G11C11/408

Abstract:
Method for performing a memory operation with respect to a memory structure having “N”-number of planes, each plane comprising “M”-number of blocks and “X”-number of word lines arranged in a serial order, and electrically connected with each plane are: a voltage bias source, an electronic switching component, and row decoder, the method comprising: with respect to each plane, selecting a block and a word line for application of the operation, wherein the operation has not been applied to the selected block and word line, the selected block of one plane is located in a different block group from the selected block of another plane, and the selected word line of one plane is in a different position within the serial order from a position of the selected word line of another plane; and using the voltage bias source, concurrently applying the operation to the selected blocks and selected word lines.
Information query
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