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公开(公告)号：US11775374B2
公开(公告)日：2023-10-03
申请号：US17231344
申请日：2021-04-15
Applicant: Western Digital Technologies, Inc.
Inventor： Liang Li , Chenxiao Xu , Qin Zhen
CPC classification number: G06F11/079 , G06F11/0727 , G06F11/0754 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3459 , H10B41/27 , H10B43/27
Abstract: Apparatuses and techniques are described for detecting a defect in a memory cell array during program operations. A defect can be detected by comparing the programming speed of memory cells connected to different word lines, for one or more programmed data states. The comparison can involve adjacent word lines in a block, or word lines in different blocks and planes. The comparison involves comparing two word lines in terms of a number of program-verify loops used to reach the programmed data states or to transition between programmed data states. If a program loop delta is not within an allowable range for one or more of the programmed data states, it can be concluded that a defect is present. The block which has the slower programming word line can be identified as a bad block.
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公开(公告)号：US20230245703A1
公开(公告)日：2023-08-03
申请号：US17589973
申请日：2022-02-01
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
CPC classification number: G11C16/08 , G11C16/0483 , H02M3/07 , G11C16/30 , G11C29/12005 , H01L25/0657
Abstract: A non-volatile memory includes memory cells, word lines connected to the memory cells, and a set of regular control gate drivers connected to the word lines. The control gate drivers include different subsets of control gate drivers that receive different sources of voltage and provide different output voltages. A redundant control gate driver, that receives the different sources of voltage and provides the different output voltages, is included that can replace any of the regular control gate drivers.
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公开(公告)号：US20220334902A1
公开(公告)日：2022-10-20
申请号：US17231344
申请日：2021-04-15
Applicant: Western Digital Technologies, Inc.
Inventor： Liang Li , Chenxiao Xu , Qin Zhen
Abstract: Apparatuses and techniques are described for detecting a defect in a memory cell array during program operations. A defect can be detected by comparing the programming speed of memory cells connected to different word lines, for one or more programmed data states. The comparison can involve adjacent word lines in a block, or word lines in different blocks and planes. The comparison involves comparing two word lines in terms of a number of program-verify loops used to reach the programmed data states or to transition between programmed data states. If a program loop delta is not within an allowable range for one or more of the programmed data states, it can be concluded that a defect is present. The block which has the slower programming word line can be identified as a bad block.
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公开(公告)号：US11908521B2
公开(公告)日：2024-02-20
申请号：US17589973
申请日：2022-02-01
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/30 , G11C29/12005 , H02M3/07 , H01L25/0657 , H01L2225/06562 , H10B43/27
Abstract: A non-volatile memory includes memory cells, word lines connected to the memory cells, and a set of regular control gate drivers connected to the word lines. The control gate drivers include different subsets of control gate drivers that receive different sources of voltage and provide different output voltages. A redundant control gate driver, that receives the different sources of voltage and provides the different output voltages, is included that can replace any of the regular control gate drivers.
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公开(公告)号：US11335419B1
公开(公告)日：2022-05-17
申请号：US17197762
申请日：2021-03-10
Applicant: Western Digital Technologies, Inc.
Abstract: An erase operation for data memory cells is integrated with a process for detecting dummy memory cells and/or select gate transistors which have an out-of-range threshold voltage. In one aspect, an erase operation is performed for the data memory cells of a block followed by a supplementary verify operation for the dummy memory cells and/or select gate transistors. In another aspect, the verify operation occurs during the erase operation and, optionally, also in a supplementary verify operation. A separate pass/fail status can be set for the erase verify of the data memory cells and the verify of the dummy memory cells and/or select gate transistors operations, where the block is assigned to a potential bad block pool or bad block pool based on a status return combination. The out-of-range dummy memory cells and/or select gate transistors can be adjusted by programming or erasing.
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公开(公告)号：US11073570B1
公开(公告)日：2021-07-27
申请号：US16885655
申请日：2020-05-28
Applicant: Western Digital Technologies, Inc.
IPC: G01R31/40
Abstract: Techniques and apparatuses are provided for testing a charge pump. A test circuit detects voltage drop-offs in a voltage signal provided by a charge pump in a test period. A comparator is used to compare the voltage signal to a divided down, delayed version of the signal. A counting circuit is connected to an output of the comparator to determine a number of the drop-offs in the test period. A control circuit such as an on-chip state machine compares the number of drop-offs to a maximum allowable number of drop-offs to set a pass/fail status of the charge pump. The control circuit can configure various parameters of the test, including a ratio of a voltage divider, and the maximum allowable number of drop-offs based on the charge pump being tested.
