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公开(公告)号:US11687252B2
公开(公告)日:2023-06-27
申请号:US17503612
申请日:2021-10-18
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Liang Li , Yinfeng Yu , Loc Tu
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679 , G06N5/04 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L25/0657 , G11C11/5671 , H01L2225/06562
Abstract: A non-volatile storage apparatus comprises one or more memory die assemblies, each of which includes an inference circuit positioned in the memory die assembly. The inference circuit is configured to use a pre-trained model (received pre-trained from a source external to the non-volatile storage apparatus and stored in a dedicated block in non-volatile memory) with one or more metrics describing current operation of the non-volatile storage apparatus in order to predict a defect in the non-volatile storage apparatus and perform a countermeasure to preserve host data prior to a non-recoverable failure in the non-volatile storage apparatus due to the defect.
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公开(公告)号:US20230048326A1
公开(公告)日:2023-02-16
申请号:US17400609
申请日:2021-08-12
Applicant: Western Digital Technologies, Inc.
Inventor: Liang Li , Qianqian Yu , Jiahui Yuan , Loc Tu
Abstract: Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.
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3.
公开(公告)号:US12099743B2
公开(公告)日:2024-09-24
申请号:US17709745
申请日:2022-03-31
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Liang Li , Loc Tu , Yinfeng Yu , Xuan Tian
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/064 , G06F3/0653 , G06F3/0679 , G06N5/04
Abstract: A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.
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4.
公开(公告)号:US20230315330A1
公开(公告)日:2023-10-05
申请号:US17709745
申请日:2022-03-31
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Liang Li , Loc Tu , Yinfeng Yu , Xuan Tian
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0653 , G06F3/0679 , G06F3/064 , G06N5/04
Abstract: A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.
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5.
公开(公告)号:US20240220130A1
公开(公告)日:2024-07-04
申请号:US18357354
申请日:2023-07-24
Applicant: Western Digital Technologies, Inc.
Inventor: Liang Li , Jiahui Yuan , Loc Tu
CPC classification number: G06F3/0616 , G06F3/0659 , G06F3/0679 , G11C16/3495
Abstract: A non-volatile memory system reduces the number of bits of data per non-volatile memory cell for a block (or other grouping of non-volatile memory cells) in response to a failed memory operation, the block being subjected to more than a minimum number of programming cycles or other events. The reducing of the number of bits of data stored in the memory cells allows the useful life of the block to be extended.
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公开(公告)号:US11756630B2
公开(公告)日:2023-09-12
申请号:US17400609
申请日:2021-08-12
Applicant: Western Digital Technologies, Inc.
Inventor: Liang Li , Qianqian Yu , Jiahui Yuan , Loc Tu
CPC classification number: G11C16/26 , G11C11/5642 , G11C11/5671 , G11C16/0483 , H10B41/27 , H10B43/27
Abstract: Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.
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公开(公告)号:US20230124035A1
公开(公告)日:2023-04-20
申请号:US17503612
申请日:2021-10-18
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Liang Li , Yinfeng Yu , Loc Tu
Abstract: A non-volatile storage apparatus comprises one or more memory die assemblies, each of which includes an inference circuit positioned in the memory die assembly. The inference circuit is configured to use a pre-trained model (received pre-trained from a source external to the non-volatile storage apparatus and stored in a dedicated block in non-volatile memory) with one or more metrics describing current operation of the non-volatile storage apparatus in order to predict a defect in the non-volatile storage apparatus and perform a countermeasure to preserve host data prior to a non-recoverable failure in the non-volatile storage apparatus due to the defect.
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