公开(公告)号：US5879970A

公开(公告)日：1999-03-09

申请号：US922577

申请日：1997-09-03

Applicant: Kunihiko Shiota ,  Jun-ichi Hanna

Inventor： Kunihiko Shiota ,  Jun-ichi Hanna

IPC: C23C16/42 ,  H01L21/205 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/0262 ,  Y10S438/935 ,  Y10S438/967 ,  Y10S438/98

Abstract: Polycrystalline silicon-germanium alloy is grown on a glass substrate through a chemical vapor deposition under the conditions where the substrate temperature ranges from 350 degrees to 450 degrees in centigrade, the ratio between gas flow rate of Si.sub.2 H.sub.6 and the gas flow rate of GeF.sub.4 ranges from 20:0.9 to 40:0.9 and the dilution gas is selected from the group consisting of helium, argon, nitrogen and hydrogen, and the composition ratio of silicon of the polycrystalline silicon-germanium is equal to or greater than 80 percent so that the carrier mobility is drastically improved.

Abstract translation: 多晶硅锗合金通过化学气相沉积在基板温度为350摄氏度至450摄氏度的条件下在玻璃基板上生长，Si2H6的气体流量与GeF4的气体流量之比为 20：0.9〜40：0.9，稀释气体选自氦气，氩气，氮气和氢气，多晶硅 - 锗的硅的组成比等于或大于80％，使载体 流动性大大提高。

公开(公告)号：US5804847A

公开(公告)日：1998-09-08

申请号：US577995

申请日：1995-12-22

Applicant: Gerald D. Robinson

Inventor： Gerald D. Robinson

IPC: H01L29/812 ,  H01L31/0352 ,  H01L31/112 ,  H01L31/18 ,  H01L29/80 ,  H01L31/0288

CPC classification number: H01L31/1844 ,  H01L29/8126 ,  H01L31/0352 ,  H01L31/1123 ,  H01L31/1126 ,  Y02E10/544 ,  Y10S438/977 ,  Y10S438/98

Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration and then inverted onto a new permanent substrate member and an original surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Electrical characteristics including curve tracer electrical data originating in both dark and illuminated devices and devices of varying size and both depletion mode and enhancement mode operation are also disclosed. Fabrication of the device from gallium arsenide semiconductor material and utilization for infrared energy transducing in a number of differing electronic applications are also disclosed.

Abstract translation: 公开了一种具有大面积背面光能接收表面的光电FET器件。 光源FET器件以源栅极和漏极向上配置制造，然后反转到新的永久性衬底构件上，并且去除原始替代衬底构件以暴露有源区域背面光能接收表面。 还公开了包括起源于暗和照明装置的曲线跟踪器电数据和不同大小以及耗尽模式和增强模式操作两者的电特性。 还公开了从砷化镓半导体材料制造器件和在许多不同的电子应用中利用红外能量转换的方法。

公开(公告)号：US5728259A

公开(公告)日：1998-03-17

申请号：US545122

申请日：1995-10-19

Applicant: Hideomi Suzawa ,  Shunpei Yamazaki ,  Toshiji Hamatani ,  Yasuhiko Takemura

Inventor： Hideomi Suzawa ,  Shunpei Yamazaki ,  Toshiji Hamatani ,  Yasuhiko Takemura

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L21/02057 ,  H01L21/30608 ,  H01L21/3065 ,  Y10S438/978 ,  Y10S438/98

Abstract: Disclosed herein is a process for fabricating a thin-film semiconductor device which includes (1) a step of etching a silicon film by wet etching or gas etching, the former employing a liquid containing hydrazine or ethylene diamine, the latter employing chlorine fluoride, thereby forming an island-like silicon semiconductor region having inclined edges, and (2) a step of forming thereon a gate insulating film by plasma-free process such as heated CVD. The process yields the island-like silicon region and gate insulating film completely free from plasma-induced damage. This reduces the leakage current between the source and drain (which is due to plasma-induced damage) and prevents the degradation of characteristic properties.

Abstract translation: 本文公开了一种制造薄膜半导体器件的方法，其包括（1）通过湿蚀刻或气蚀刻蚀硅膜的步骤，前者采用含有肼或乙二胺的液体，后者采用氯氟化物 形成具有倾斜边缘的岛状硅半导体区域，以及（2）通过无等离子体工艺（例如加热CVD）在其上形成栅极绝缘膜的步骤。 该工艺使岛状硅区和栅极绝缘膜完全没有等离子体引起的损伤。 这减少了源极和漏极之间的泄漏电流（这是由于等离子体引起的损坏），并且防止了特性的降低。

公开(公告)号：US5707879A

公开(公告)日：1998-01-13

申请号：US780584

申请日：1997-01-08

Applicant: Karl Reinitz

Inventor： Karl Reinitz

IPC: G01T3/06 ,  G01T3/08 ,  H01L21/26 ,  H01L31/0288 ,  H01L31/115

CPC classification number: G01T3/08 ,  G01T3/06 ,  Y10S148/04 ,  Y10S438/98

Abstract: A neutron radiation detector is described. A semiconductor material is populated with helium three (.sup.3 He) atoms to increase its overall neutron capture efficiency. Upon capture of a neutron by a .sup.3 He atom, a tritium ion and a proton are generated with energies of 0.191 and 0.573 MeV, respectively. These energies are deposited in the semiconductor material creating electron-hole pairs. The electron-hole pairs are withdrawn from the material by the application of an electric field and are collected as charges at the terminals. The associated circuitry processes the charges into pulses with these being counted and their sizes measured. The results are recorded and displayed. The number of pulses are a measure of the number of neutrons absorbed in the detector and of the neutron flux of interest. In many instances the detector can also be used to detect and display non-neutron type radiation or simultaneously neutron and non-neutron forms of radiative activity.

Abstract translation: 描述了中子辐射检测器。 半导体材料填充有氦三（3He）原子以增加其整体中子捕获效率。 当用3He原子捕获中子时，分别产生氚离子和质子，能量分别为0.191和0.573MeV。 这些能量沉积在产生电子 - 空穴对的半导体材料中。 电子 - 空穴对通过施加电场从材料中取出，并在端子处收集作为电荷。 相关的电路将电荷处理成脉冲，并将其计数并测量它们的尺寸。 记录和显示结果。 脉冲的数量是在检测器中吸收的中子数量和感兴趣的中子通量的量度。 在许多情况下，检测器也可用于检测和显示非中子型辐射或同时中子和非中子形式的辐射活动。

公开(公告)号：US5575886A

公开(公告)日：1996-11-19

申请号：US503088

申请日：1995-07-17

Applicant: Hiroshi Murase

Inventor： Hiroshi Murase

IPC: C23C16/50 ,  B24B37/04 ,  C23C16/511 ,  H01L21/304 ,  H01L21/306 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L21/00

CPC classification number: B24B37/042 ,  H01L21/31053 ,  H01L21/76819 ,  Y10S438/98

Abstract: The method for fabricating a semiconductor device disclosed is one in which an insulation film is formed on a metal interconnect by an Electron Cyclotron Resonance Chemical Vapor Deposition (ECR CVD) process capable of applying a radio frequency bias to a substrate, a surface of the insulation film is planarized by a chemical-mechanical polishing (CMP) process, and a surface of the insulation film is cleaned. The ECR CVD process capable of applying a radio frequency bias to a substrate may be a radio frequency bias plasma CVD process or a bias sputtering process. The cleaning of the surface of the insulation film may use a hydrogen fluoride solution. It is easy to control processes without increasing the number of process steps and a high degree of planarization can be realized.

Abstract translation: 所公开的制造半导体器件的方法是其中通过能够对衬底施加射频偏压的电子回旋加速度共振化学气相沉积（ECR CVD）工艺在金属互连上形成绝缘膜，绝缘层的表面 通过化学机械抛光（CMP）工艺将膜平坦化，并且清洁绝缘膜的表面。 能够对基板施加射频偏压的ECR CVD工艺可以是射频偏置等离子体CVD工艺或偏压溅射工艺。 绝缘膜的表面的清洁可以使用氟化氢溶液。 在不增加处理步骤的数量的情况下容易地控制处理，并且可以实现高度的平坦化。

公开(公告)号：US5567644A

公开(公告)日：1996-10-22

申请号：US528124

申请日：1995-09-14

Applicant: J. Brett Rolfson ,  Monte Manning

Inventor： J. Brett Rolfson ,  Monte Manning

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11

CPC classification number: H01L28/20 ,  H01L21/76888 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S438/98

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract translation: 公开了从半导体材料形成电阻器和二极管的方法，以及结合电阻器的静态随机存取存储器（SRAM）单元以及并入电阻器和二极管的集成电路的方法。 提供要进行电连接的节点。 在节点外部设置一个电绝缘层。 在节点上的电绝缘层中设置开口。 开口填充有半导体材料，其取决于配置用作垂直细长的二极管和电阻器中的一个或两个。

公开(公告)号：US5328549A

公开(公告)日：1994-07-12

申请号：US845006

申请日：1992-03-03

Applicant: Carl O. Bozler ,  John C. C. Fan ,  Robert W. McClelland

Inventor： Carl O. Bozler ,  John C. C. Fan ,  Robert W. McClelland

IPC: C30B25/04 ,  C30B33/00 ,  H01L21/20 ,  H01L25/04 ,  H01L31/0687 ,  H01L31/18 ,  H01S5/02

CPC classification number: H01L31/0687 ,  C30B25/04 ,  C30B29/60 ,  C30B33/00 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/2007 ,  H01L31/043 ,  H01L31/18 ,  H01L31/1804 ,  H01L31/184 ,  H01L2924/0002 ,  H01S5/0207 ,  H01S5/0217 ,  Y02E10/544 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S117/915 ,  Y10S438/98

Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.

公开(公告)号：US5210045A

公开(公告)日：1993-05-11

申请号：US862474

申请日：1992-05-18

Applicant: George E. Possin ,  Harold G. Parks ,  Jack D. Kingsley

Inventor： George E. Possin ,  Harold G. Parks ,  Jack D. Kingsley

IPC: H01L27/12

CPC classification number: H01L27/12 ,  Y10S148/043 ,  Y10S438/98

Abstract: A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electrical and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield. As display sizes increase, the yield problem becomes more and more significant, generally growing as the square of the diagonal measurement of the screen. The structure in the present invention also significantly reduces gate leakage current. In the process and structure of the present invention, gate electrode material is separated from semiconductor material by the aforementioned dual dielectric, typically comprising layers of silicon oxide disposed beneath a layer of silicon nitride which is, in turn, disposed beneath the active amorphous silicon semiconductor material.

Abstract translation: 双电介质结构用于在矩阵寻址液体显示器中制造薄膜场效应晶体管以提供改进的晶体管器件特性，并且还为栅极金属化层中所采用的材料提供电和化学隔离。 特别地，在栅极金属化层上使用一层氧化硅不仅与提供期望的电和化学隔离一致，而且还提供要用于电路冗余的源极或数据线下方的冗余栅极金属化材料。 栅线冗余也是可能的。 由双电介质层提供的电气和化学隔离减少了在显示器中发生短路的可能性。 没有短路以及改进的冗余特性显着提高了制造产量。 随着显示尺寸的增加，产量问题变得越来越重要，通常随屏幕对角线测量的平方而增长。 本发明的结构也显着地降低了栅极漏电流。 在本发明的方法和结构中，栅极电极材料通过上述双电介质与半导体材料分离，所述双电介质通常包括设置在有源非晶硅半导体下方的氮化硅层下方的氧化硅层 材料。

公开(公告)号：US5120676A

公开(公告)日：1992-06-09

申请号：US498868

申请日：1990-03-23

Applicant: Andreas A. Melas ,  Ravi K. Kanjolia ,  Ben C. Hui

Inventor： Andreas A. Melas ,  Ravi K. Kanjolia ,  Ben C. Hui

IPC: C23C16/30 ,  C30B25/02

CPC classification number: C30B25/02 ,  C23C16/301 ,  C30B29/40 ,  C30B29/48 ,  Y10S252/951 ,  Y10S438/98

Abstract: A MOCVD process for depositing an arsenic-containing film or a phosphorous-containing film utilizing a diprimary phosphine or arsine or an unsaturated hydrocarbon phosphine or arsine.

Abstract translation: 一种利用二原子膦或胂或不饱和烃膦或胂来沉积含砷膜或含磷膜的MOCVD方法。

公开(公告)号：US4626322A

公开(公告)日：1986-12-02

申请号：US740182

申请日：1985-05-31

Applicant: Jay A. Switzer

Inventor： Jay A. Switzer

IPC: H01L27/142 ,  H01L31/02 ,  H01L31/074 ,  C25D9/04 ,  H01L31/18

CPC classification number: H01L31/074 ,  C25D5/006 ,  H01L31/02021 ,  H01L31/0475 ,  Y02E10/50 ,  Y10S204/03 ,  Y10S205/915 ,  Y10S438/98

Abstract: A solid-state semiconductor photonic device is prepared by a photoelectrochemical deposition method. The device contains a highly conductive coating material including one or more metals and/or semiconductors on a substrate containing a semiconductor material. The device is utilized in photodetectors, including radiometric detection cells, in conversions of electrical energy to optical radiation, such as light-emitting-diodes and diodes lasers, and in photovoltaic cells, including Schottky-barrier cells.

Abstract translation: 通过光电化学沉积方法制备固态半导体光子器件。 该器件包含在包含半导体材料的衬底上包括一种或多种金属和/或半导体的高导电性涂层材料。 该装置用于光电检测器，包括辐射测量单元，将电能转换成光辐射，例如发光二极管和二极管激光器，以及包括肖特基势垒电池在内的光伏电池中。