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    POWER SEMICONDUCTOR DEVICE
    31.
    发明申请
    POWER SEMICONDUCTOR DEVICE 有权
    功率半导体器件

    公开(公告)号：US20160300785A1

    公开(公告)日：2016-10-13

    申请号：US15037388

    申请日：2013-12-05

    申请人： Mitsubishi Electric Corporation

    发明人： Toru Kimura ,  Yoichi Goto ,  Kiyofumi Kitai

    IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/492 ,  H01L23/367

    CPC分类号： H01L23/49568 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/4924 ,  H01L23/49541 ,  H01L23/49565 ,  H01L24/32 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/32245 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/00

    摘要： Projections 35 provided in a base plate 22 are fitted into notches provided in an electrically conductive member 12, and then the base plate 22 is fixed to the electrically conductive member 12 by deforming the projections 35 and the electrically conductive member 12 is connected to earth ground, so that noise radiated from a power semiconductor element 21 is reduced and malfunction of the power semiconductor element 21 is suppressed.A power semiconductor device is provided with: the base plate 22 that is thermally connected to the power semiconductor element 21 so as for heat generated from the power semiconductor element 21 to be conducted to heat radiation fins 11; and the electrically conductive member 12 that is fixed to the base plate 22, is electrically conducted to the base plate 22, and is connected to earth ground, wherein the projections 35 provided in the base plate 22 are fitted into notches provided in the electrically conductive member 12, and by deforming the projections 35, the electrically conductive member 12 is fixed to the base plate 22 and electrical conduction can be secured.

    摘要翻译： 功率半导体器件设置有：与功率半导体元件21热连接的基板22，以便从功率半导体元件21产生的热量传导到散热片11; 并且固定到基板22的导电构件12被导电到基板22，并且连接到接地，其中设置在基板22中的突起35被配合到设置在导电中的凹口中 构件12，并且通过使突起35变形，导电构件12固定到基板22上，并且可以确保导电。

    LIGHT EMITTING MODULE AND LIGHT UNIT HAVING THE SAME
    32.
    发明申请
    LIGHT EMITTING MODULE AND LIGHT UNIT HAVING THE SAME 有权
    发光模块和具有相同功能的灯具

    公开(公告)号：US20160230943A1

    公开(公告)日：2016-08-11

    申请号：US15015916

    申请日：2016-02-04

    申请人： LG INNOTEK CO., LTD.

    发明人： Mi Na SHIN ,  Eon Ho SON ,  Young Joo AHN

    IPC分类号： F21K99/00 ,  F21V23/00

    CPC分类号： F21V23/001 ,  F21K9/00 ,  F21K9/20 ,  F21Y2101/00 ,  F21Y2105/10 ,  F21Y2105/12 ,  F21Y2113/13 ,  F21Y2115/10 ,  H01L25/00 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

    摘要： Disclosed is a light emitting module including a circuit board and a light source unit disposed on the circuit board. The light source unit includes a plurality of first, second and third light emitting devices emitting light of different colors, the plurality of first light emitting devices are disposed in an outer circumference of the second and third light emitting devices, the plurality of second light emitting devices are disposed in both sides of the plurality of the third light emitting devices, the plurality of first light emitting devices emits light having a wavelength longer than that of light emitted from the second and third light emitting devices. The plurality of second light emitting devices emits light having a wavelength longer than that of light emitted from the third light emitting devices, and the numbers of the first to third light emitting devices are different from one another.

    摘要翻译： 公开了一种发光模块，包括设置在电路板上的电路板和光源单元。 光源单元包括发射不同颜色的光的多个第一，第二和第三发光器件，多个第一发光器件设置在第二和第三发光器件的外周中，多个第二发光器件 设置在多个第三发光器件的两侧，多个第一发光器件发射的波长比从第二和第三发光器件发射的光的波长长。 多个第二发光器件发射的波长比从第三发光器件发射的光的波长更长，并且第一至第三发光器件的数量彼此不同。

    Heterogeneous programmable device and configuration software adapted therefor
    33.
    发明授权
    Heterogeneous programmable device and configuration software adapted therefor 有权

    公开(公告)号：US09401718B1

    公开(公告)日：2016-07-26

    申请号：US14681419

    申请日：2015-04-08

    申请人： Altera Corporation

    发明人： David Lewis ,  Valavan Manohararajah ,  David Galloway

    IPC分类号： H03K19/177

    CPC分类号： H03K19/177 ,  G06F17/5054 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

    Abutment structure of semiconductor cell
    36.
    发明授权
    Abutment structure of semiconductor cell 有权
    半导体电池基台结构

    公开(公告)号：US09299683B2

    公开(公告)日：2016-03-29

    申请号：US13675540

    申请日：2012-11-13

    申请人： Jye-Yuan Lee

    发明人： Yi-Fon Chen ,  Yu-Cheng Yang ,  Jye-Yuan Lee

    IPC分类号： H01L23/52 ,  H01L25/00 ,  H01L27/02 ,  H01L27/118

    CPC分类号： H01L25/00 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An abutment structure comprises a power rail, a ground rail parallel to the power rail, first cells and second cells. An area is defined between the power and the ground rails. A portion of each first and second cell overlaps the power and the ground rails, and another portion thereof is within the area. The first cells are within the abutment structure with original patterns thereof. The second cells respectively has an original pattern and a base pattern being a flip pattern of the original pattern, and are within the area with alternate of the original and the base patterns. The first and the second cells are within the area alternately without overlapping. Alternatively, the first and the second cells may also be within different areas, and the second cells are within different areas respectively with the base pattern and a flip pattern of the base pattern thereof.

    摘要翻译： 邻接结构包括电力轨道，平行于电力轨道的接地轨道，第一单元和第二单元。 在电源和接地导轨之间定义一个区域。 每个第一和第二电池的一部分与功率和接地导轨重叠，并且其另一部分在该区域内。 第一个细胞位于具有其原始图案的邻接结构内。 第二单元分别具有原始图案，并且基本图案是原始图案的翻转图案，并且在原始图案和基本图案的交替区域内。 第一和第二电池在该区域内交替地不重叠。 或者，第一和第二单元也可以在不同的区域内，并且第二单元分别在不同的区域内具有基本图案和其基本图案的翻转图案。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    37.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20160079250A1

    公开(公告)日：2016-03-17

    申请号：US14645793

    申请日：2015-03-12

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Yoshihiro AKUTSU ,  Ryota Katsumata

    IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L27/11556 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

    摘要翻译： 该非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括在与半导体衬底的表面垂直的第一方向上形成的NAND单元单元。 局部源极线电耦合到形成在衬底表面上的NAND单元单元的一端。 存储单元阵列包括：层叠体，其中将要控制存储单元的栅极线的多个导电膜或选择晶体管的选择栅极线层叠夹层层间绝缘膜; 半导体层，其沿所述第一方向延伸; 以及夹在所述半导体层和所述导电膜之间的电荷蓄积层。 本地源极线包括硅化物层。 电荷累积层由存储单元阵列连续地形成以覆盖硅化物层的周边区域。

    Method for fabricating embedded chips
    40.
    发明授权
    Method for fabricating embedded chips 有权
    嵌入式芯片的制造方法

    公开(公告)号：US09240392B2

    公开(公告)日：2016-01-19

    申请号：US14249282

    申请日：2014-04-09

    申请人： Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

    发明人： Dror Hurwitz ,  Alex Huang

    IPC分类号： H01L25/00 ,  H01L25/075 ,  H01L25/07 ,  H01L25/065 ,  H01L25/04

    CPC分类号： H01L25/00 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/042 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L2224/04105 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2933/005 ,  H01L2924/00

    摘要： A method of fabricating embedded die packages including the following steps: obtaining a honeycomb array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket; placing the honeycomb array on a transparent tape so that an underside of the honey comb array contacts the transparent tape; positioning a chip terminal the down (flip chip) in each chip socket so that undersides of the dies contact the transparent tape; using optical imaging through the tape to align the chips with the via posts; applying a packing material over and around the chips in the honeycomb array, and curing the filler to embed the chips on five sides; thinning and planarizing the packing material to expose upper ends of the vias on upper side of the array; removing the transparent tape; applying a feature layer of conductors on the underside of the honeycomb array and the undersides of the chips, to couple at least one terminal of each die to at least one through via; applying a feature layer of conductors on over side of the honeycomb array such that at least one conductor extends from a through via at least partway over each chip; dicing the array to create separate dies comprising at least one embedded chip having a contract pad coupled to a through via adjacent the chip.

    摘要翻译： 一种制造嵌入式管芯封装的方法，包括以下步骤：获得芯片插座的蜂窝阵列，使得每个芯片插座由具有第一聚合物的聚合物基体的框架和穿过框架围绕每个插座的至少一个通孔支架围绕; 将蜂窝状阵列放置在透明胶带上，使得蜂巢梳状阵列的下侧接触透明带; 将芯片端子放置在每个芯片插座中，使芯片的下侧与透明胶带接触; 使用通过胶带的光学成像将芯片与通孔柱对准; 将包装材料涂覆在蜂窝状阵列上的芯片周围，并固化填料以将芯片嵌入五面; 使包装材料变薄并平坦化，以暴露阵列上侧通孔的上端; 去除透明胶带; 在蜂窝阵列的下侧和芯片的下侧上施加导体的特征层，以将每个管芯的至少一个端子耦合到至少一个通孔; 在所述蜂窝状阵列的上侧上施加导体的特征层，使得至少一个导体至少在每个芯片的一半上从通孔延伸; 对所述阵列进行切割以形成分开的裸片，其包括至少一个嵌入式芯片，所述至少一个嵌入式芯片具有耦合到邻近所述芯片的通孔的合约焊盘。