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公开(公告)号：US20180089024A1
公开(公告)日：2018-03-29
申请号：US15274037
申请日：2016-09-23
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Judah Gamliel Hahn , Gadi Vishne , Joshua Lehmann , Alexander Bazarsky , Ariel Navon
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1048 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/32 , G11C29/021 , G11C29/028 , G11C2029/0409 , H04L1/0015 , H04L1/0017 , H04L1/0025 , H04L1/0026 , H04L1/004 , H04L29/06523 , H04L41/5022 , H04L41/5025
Abstract: A non-volatile memory system receives a request to read data. That request includes a quality of service indication. The memory system performs a read process that satisfies the quality of service indication and identifies a set of data with errors. The memory system returns the set of data with errors in response to the request.
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公开(公告)号：US09911509B2
公开(公告)日：2018-03-06
申请号：US14099551
申请日：2013-12-06
Applicant: Intel Corporation
Inventor： Ravi H. Motwani
CPC classification number: G11C29/44 , G11C29/42 , G11C29/82 , G11C2029/0409 , G11C2029/0411
Abstract: Methods and apparatus related to utilization of counter(s) for locating faulty die in a distributed codeword storage system are described. In one embodiment, first logic determines a plurality of values. Each of the plurality of values corresponds to a number of zeros or a number of ones in bits read from a portion of each of a plurality of memory dies. Second logic determines one or more candidates as a faulty die amongst the plurality of memory dies based at least in part on a comparison of the plurality of values for the plurality of memory dies. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180062668A1
公开(公告)日：2018-03-01
申请号：US15666705
申请日：2017-08-02
Inventor： Jaekyun MOON , Beongjun CHOI , Sung Whan YOON
CPC classification number: H03M13/2906 , G06F11/1012 , G06F11/1068 , G11C29/021 , G11C29/028 , G11C29/50004 , G11C29/52 , G11C2029/0409 , H03M13/09 , H03M13/3707
Abstract: An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.
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公开(公告)号：US20180061474A1
公开(公告)日：2018-03-01
申请号：US15467360
申请日：2017-03-23
Applicant: SK hynix Inc.
Inventor： Min Seok CHOI
IPC: G11C11/408 , G11C11/406 , G11C11/4076 , G06F3/06 , G06F11/10 , G11C29/52
CPC classification number: G11C11/408 , G06F3/0619 , G06F3/0653 , G06F3/0673 , G06F11/106 , G06F11/1068 , G11C7/04 , G11C8/12 , G11C11/40615 , G11C11/4076 , G11C29/52 , G11C2029/0409 , G11C2029/0411
Abstract: A semiconductor device includes a bank address generation circuit, a row/column address generation circuit, and an operation control circuit. The bank address generation circuit generates a bank address signal according to a bank group selection signal which is generated in response to a first temperature code and a second temperature code. The row/column address generation circuit generates a row address signal and a column address signal according to an area selection signal which is generated in response to a third temperature code and a fourth temperature code. The operation control circuit performs a data scrub operation on a cell which is accessed by the bank address signal, the row address signal and the column address signal.
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公开(公告)号：US20180047444A1
公开(公告)日：2018-02-15
申请号：US15663527
申请日：2017-07-28
Applicant: SK Hynix Memory Solutions Inc.
Inventor： David PIGNATELLI , Fan ZHANG
CPC classification number: G11C11/5642 , G06F3/0614 , G06F3/0647 , G06F3/0653 , G06F3/0679 , G11C16/0458 , G11C16/0483 , G11C16/26 , G11C16/28 , G11C29/021 , G11C29/028 , G11C29/52 , G11C29/76 , G11C2029/0409 , G11C2029/0411
Abstract: An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled to the plurality of memory devices, wherein the controller is configured to perform a symmetric OVS read with at least an initial read threshold, and create a symmetric read result; perform an asymmetric OVS read with at least the initial read threshold, and create an asymmetric read result; adjust the initial read threshold according to at least the symmetric read result and asymmetric read result, and create an optimal read threshold; and execute data recovery process with the optimal read threshold.
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Patent Agency Ranking
公开(公告)号：US09891990B2
公开(公告)日：2018-02-13
申请号：US14835011
申请日：2015-08-25
Applicant: International Business Machines Corporation
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0625 , G06F3/064 , G06F3/0652 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F11/106 , G11C29/52 , G11C29/74 , G11C2029/0409
Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.
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公开(公告)号：US20180039578A1
公开(公告)日：2018-02-08
申请号：US15652259
申请日：2017-07-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： EUN-JIN YUN , SIL WAN CHANG
IPC: G06F12/1009 , G06F11/10 , G11C29/52 , G06F3/06
CPC classification number: G06F12/1009 , G06F3/0619 , G06F3/0631 , G06F3/065 , G06F3/0653 , G06F3/0656 , G06F3/0659 , G06F3/0688 , G06F11/1048 , G06F11/1068 , G06F12/0246 , G06F2212/1024 , G06F2212/65 , G06F2212/7201 , G11C29/52 , G11C2029/0409
Abstract: A method of operating a data storage device in which a nonvolatile memory is included and a mapping table defining a mapping relation between a physical address and a logical address of the nonvolatile memory is stored in a host memory buffer of a host memory includes requesting a host for an asynchronous event based on information about a map miss that the mapping relation about the logical address received from the host is not included in the mapping table, receiving information about the host memory buffer adjusted by the host based on the asynchronous event, and updating the mapping table to the adjusted host memory buffer with reference to the information about the host memory buffer. A method of operating a data storage device according to example embodiments of the inventive concept can reduce the number of map misses or improve reliability of a nonvolatile memory.
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38.发明申请公开(公告)号：US20180033491A1
公开(公告)日：2018-02-01
申请号：US15655639
申请日：2017-07-20
Applicant: IP GEM GROUP, LLC
Inventor： Alessia Marelli , Rino Micheloni
CPC classification number: G11C16/26 , G06F11/076 , G11C11/5642 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/26 , G11C29/4401 , G11C29/46 , G11C29/50004 , G11C29/50016 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C2029/1202 , G11C2029/4402 , G11C2029/5002
Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.
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公开(公告)号：US20180032396A1
公开(公告)日：2018-02-01
申请号：US15223302
申请日：2016-07-29
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： ERAN SHARON , STELLA ACHTENBERG
CPC classification number: G06F3/0679 , G06F3/0619 , G06F3/064 , G06F11/1048 , G11C11/5642 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , H03M13/3715 , H03M13/3738 , H03M13/6337
Abstract: A device includes a memory device and a controller. The controller is configured to determine, based on data read from the memory device, a first count of bits of the data that are associated with at least a first number of unsatisfied parity checks of the data and a second count of bits of the data that are associated with at least a second number of unsatisfied parity checks of the data. The controller is further configured to perform one or more operations based at least partially on the first count and the second count.
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公开(公告)号：US09871624B2
公开(公告)日：2018-01-16
申请号：US15244196
申请日：2016-08-23
Applicant: FUJITSU LIMITED
Inventor： Hiroaki Shiraishi , Tateo Shimaru , Naoyuki Takeshita , Katsuhiko Hirashima , Masaru Nishida , Tsuneharu Suzuki , Hisaya Urabe
CPC classification number: H04L1/08 , G06F11/00 , G06F11/0709 , G06F13/4059 , G11C29/022 , G11C2029/0409
Abstract: A transmission apparatus includes a first storage configured to store data received from external into a write enable area, a second storage configured to store the data in accordance with a write request and output a retry request in response to occurring an error of writing a first data included in the data, and a controller configured to read the data from the first storage and send the write request to the second storage, set an area of the first storage storing the first data to a write disable area in combination with stop sending the retry request to external when receiving the retry request from the second storage, and send the first data reading from the write disable area of the first storage to external in response to a read request from external.
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