Error correction code processing and data shaping for reducing wear to a memory

    公开(公告)号:US10114549B2

    公开(公告)日:2018-10-30

    申请号:US15073373

    申请日:2016-03-17

    Abstract: A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.

    Immediate feedback before or during programming
    4.
    发明授权
    Immediate feedback before or during programming 有权
    编程前或编程过程中的即时反馈

    公开(公告)号:US09583196B2

    公开(公告)日:2017-02-28

    申请号:US14607408

    申请日:2015-01-28

    Abstract: A system and method of programming user data into a memory cell includes receiving a first user data to be programmed in a memory controller, selecting a memory cell for programming the first user data and measuring at least one health characteristic of the selected memory cell. At least one programming parameter of the selected memory cell is adjusted and the first user data is programmed to the selected memory cell using the adjusted programming parameter corresponding to the selected memory cell.

    Abstract translation: 将用户数据编程到存储器单元中的系统和方法包括:接收要在存储器控制器中编程的第一用户数据,选择用于编程第一用户数据的存储单元并测量所选存储单元的至少一个健康特性。 调整所选存储单元的至少一个编程参数,并且使用对应于所选择的存储单元的经调整的编程参数将第一用户数据编程到所选存储单元。

    Soft bit techniques for a data storage device

    公开(公告)号:US10474525B2

    公开(公告)日:2019-11-12

    申请号:US14823747

    申请日:2015-08-11

    Abstract: A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.

    BER model evaluation
    6.
    发明授权

    公开(公告)号:US10191799B2

    公开(公告)日:2019-01-29

    申请号:US15394429

    申请日:2016-12-29

    Abstract: A memory system is configured to perform a test operation to determine a deviation of a target storage location's bit error rate response relative to a model. The memory system determines the deviation level by measuring data sets stored in the target storage location to determine an actual bit error rate value and another actual parameter value used to estimate bit error rate. The memory system obtains an estimated value from the model based on the actual values and identifies the deviation by comparing the estimated value with the actual values.

    ECC decoder having adjustable parameters

    公开(公告)号:US10250281B2

    公开(公告)日:2019-04-02

    申请号:US15395185

    申请日:2016-12-30

    Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.

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