公开(公告)号：US20180032396A1

公开(公告)日：2018-02-01

申请号：US15223302

申请日：2016-07-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ERAN SHARON ,  STELLA ACHTENBERG

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C11/56

CPC classification number: G06F3/0679 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048 ,  G11C11/5642 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/3715 ,  H03M13/3738 ,  H03M13/6337

Abstract: A device includes a memory device and a controller. The controller is configured to determine, based on data read from the memory device, a first count of bits of the data that are associated with at least a first number of unsatisfied parity checks of the data and a second count of bits of the data that are associated with at least a second number of unsatisfied parity checks of the data. The controller is further configured to perform one or more operations based at least partially on the first count and the second count.

公开(公告)号：US20180034477A1

公开(公告)日：2018-02-01

申请号：US15223531

申请日：2016-07-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： RAN ZAMIR ,  ALEXANDER BAZARSKY ,  STELLA ACHTENBERG ,  OMER FAINZILBER ,  ERAN SHARON

IPC: H03M13/11 ,  G11C16/16 ,  H03M13/29 ,  G11C16/10 ,  G06F11/10 ,  G11C16/08 ,  G11C16/26

CPC classification number: H03M13/116 ,  G06F11/1076 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H03M13/1105 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1131 ,  H03M13/1171 ,  H03M13/6561

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

公开(公告)号：US20180062666A1

公开(公告)日：2018-03-01

申请号：US15244444

申请日：2016-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： XINMIAO ZHANG ,  ALEXANDER BAZARSKY ,  RAN ZAMIR ,  ERAN SHARON ,  IDAN ALROD ,  OMER FAINZILBER ,  SANEL ALTERMAN

IPC: H03M13/11 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C2029/0411 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/116 ,  H03M13/6502 ,  H03M13/6577

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

公开(公告)号：US20170255517A1

公开(公告)日：2017-09-07

申请号：US15177822

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： STELLA ACHTENBERG ,  ERAN SHARON ,  IDAN ALROD

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0644 ,  G06F11/1012 ,  G06F11/108 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/3707

Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The controller includes a stripe generator and a stripe decoder. The stripe generator is configured, in response to the number of undecodable codewords exceeding an erasure correction capacity of a stripe correction scheme, to generate trial data for a stripe of the data structure, the trial data including at least one element that corresponds to erased data and at least another element that is associated with an undecodable codeword and that corresponds to valid data of the stripe. The stripe decoder is configured to initiate a stripe decode operation of the trial data.

公开(公告)号：US20180173655A1

公开(公告)日：2018-06-21

申请号：US15385324

申请日：2016-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： STELLA ACHTENBERG ,  ERAN SHARON ,  RAN ZAMIR ,  AMIR SHAHARABANY

IPC: G06F13/16 ,  G06F13/40 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  H03M13/00 ,  G06F3/06

CPC classification number: G06F13/1689 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0679 ,  G06F11/1068 ,  G06F13/1673 ,  G06F13/4068 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  H03M13/1105 ,  H03M13/6337

Abstract: In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.

公开(公告)号：US20180159553A1

公开(公告)日：2018-06-07

申请号：US15366859

申请日：2016-12-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ERAN SHARON ,  IDAN GOLDENBERG ,  ISHAI ILANI ,  IDAN ALROD ,  YURI RYABININ ,  YAN DUMCHIN ,  MARK FITERMAN ,  RAN ZAMIR

IPC: H03M13/11 ,  G06F3/06 ,  G06F11/10 ,  H03M13/37

CPC classification number: H03M13/1111 ,  G06F11/1076 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/3707 ,  H03M13/616 ,  H03M13/6502 ,  H03M13/6508 ,  H03M13/6511 ,  H03M13/6561 ,  H03M13/6577

Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.

公开(公告)号：US20170255518A1

公开(公告)日：2017-09-07

申请号：US15177887

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： STELLA ACHTENBERG ,  ERAN SHARON ,  IDAN ALROD

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0644 ,  G06F11/1012 ,  G06F11/108 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2957 ,  H03M13/6325

Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The data structure further includes stripe parity corresponding to portions of the codewords encoded according to a stripe correction scheme. The controller is configured, in response to the number of the undecodable codewords exceeding an erasure correction capacity of the stripe correction scheme, to provide information from a stripe decoding operation to an input of a ECC decoding operation corresponding to an undecodable codeword.

公开(公告)号：US20180191381A1

公开(公告)日：2018-07-05

申请号：US15395185

申请日：2016-12-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： STELLA ACHTENBERG ,  OMER FAINZILBER ,  ARIEL NAVON ,  ALEXANDER BAZARSKY ,  ERAN SHARON

IPC: H03M13/37 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F3/06

CPC classification number: H03M13/3707 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1105 ,  H03M13/3723 ,  H03M13/6325 ,  H03M13/6511

Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.

公开(公告)号：US20170257117A1

公开(公告)日：2017-09-07

申请号：US15179069

申请日：2016-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： IDAN GOLDENBERG ,  ALEXANDER BAZARSKY ,  STELLA ACHTENBERG ,  ISHAI ILANI ,  ERAN SHARON

IPC: H03M13/11 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/1154 ,  G06F11/1012

Abstract: In an illustrative example, a method includes receiving data to be processed in accordance with a convolutional low-density parity-check (CLDPC) code. The method also includes processing the data based on a parity check matrix associated with the CLDPC code. The parity check matrix includes a first portion and a second portion. The first portion includes a plurality of copies of a first sub-matrix that is associated with a first sub-code, and the second portion includes a copy of second sub-matrix that is associated with a second sub-code.

公开(公告)号：US20170148510A1

公开(公告)日：2017-05-25

申请号：US15396495

申请日：2016-12-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ALEXANDER BAZARSKY ,  ERAN SHARON ,  ARIEL NAVON

IPC: G11C11/56 ,  G06F11/10 ,  G11C29/50 ,  G11C29/52

CPC classification number: G11C11/5642 ,  G06F11/1048 ,  G11C7/14 ,  G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5004

Abstract: A method performed in a data storage device includes reading first representations of data from a non-volatile memory according to multiple sets of read voltages. A first set of read voltages are selected based on the first representations. The method also include generating reliability information that is based on a first generated representation of the data and a second generated representation of the data. The first generated representation of the data corresponds to reading the data from the non-volatile memory according to the first set of read voltages, and the second generated representation of the data corresponds to reading the data from the non-volatile memory according to a second set of read voltages that are offset from the first set of read voltages.