公开(公告)号：US20240143528A1

公开(公告)日：2024-05-02

申请号：US17979013

申请日：2022-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Eliav Bar-Ilan ,  Ran Avraham Koren ,  Liran Liss ,  Oren Duer ,  Shahaf Shuler

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0024

Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.

公开(公告)号：US20240126699A1

公开(公告)日：2024-04-18

申请号：US18190135

申请日：2023-03-27

Applicant: SK hynix Inc.

Inventor： Sung Woo HYUN

IPC: G06F12/0862 ,  G06F12/0804 ,  G06F13/42

CPC classification number: G06F12/0862 ,  G06F12/0804 ,  G06F13/4221

Abstract: Provided herein may be a memory system and a host device. The memory system may include a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface. The second memory module may include a memory device configured to store data and a memory controller configured to update at least one of first metadata related to a space-locality and second metadata related to a time-locality based on a result of comparing the numbers of the pages respectively corresponding to a first trigger address and a second trigger address sequentially input from the host, and to prefetch, to the first memory module, the data determined based on the first metadata and the second metadata. The first and second trigger addresses are addresses corresponding to data for which access to the first memory module is missed.

公开(公告)号：US20240121180A1

公开(公告)日：2024-04-11

申请号：US18544791

申请日：2023-12-19

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Duncan Roweth ,  Andrew S. Kopser ,  Igor Gorodetsky ,  Laurence Scott Kaplan ,  Krishna Chaitanya Kandalla

IPC: H04L45/28 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1045 ,  G06F13/14 ,  G06F13/16 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173 ,  H04L1/00 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/00 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/12 ,  H04L45/122 ,  H04L45/125 ,  H04L45/16 ,  H04L45/24 ,  H04L45/42 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/10 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L47/52 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/78 ,  H04L47/80 ,  H04L49/00 ,  H04L49/101 ,  H04L49/15 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40

CPC classification number: H04L45/28 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/6235 ,  H04L47/626 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A network interface controller (NIC) capable of efficient operation management for host accelerators is provided. The NIC can be equipped with a host interface and triggering logic block. During operation, the host interface can couple the NIC to a host device. The triggering logic block can obtain, via the host interface from the host device, an operation associated with an accelerator of the host device. The triggering logic block can determine whether a triggering condition has been satisfied for the operation based on an indicator received from the accelerator. If the triggering condition has been satisfied, the triggering logic block can obtain a piece of data generated from the accelerator from a memory location and execute the operation using the piece of data.

公开(公告)号：US11954058B2

公开(公告)日：2024-04-09

申请号：US17747151

申请日：2022-05-18

Applicant: Futurewei Technologies, Inc.

Inventor： Wesley Shao

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4045 ,  G06F13/4221 ,  G06F2213/0026

Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

公开(公告)号：US11947469B2

公开(公告)日：2024-04-02

申请号：US17675897

申请日：2022-02-18

Applicant: XILINX, INC.

Inventor： Cheng Zhen ,  Sonal Santan ,  Min Ma ,  Chien-Wei Lan

IPC: G06F13/10 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Embodiments herein describe partitioning an acceleration device based on the needs of each user application executing in a host. In one embodiment, a flexible queue provisioning method allows the acceleration device to be dynamically partitioned by pushing the configuration through a control command queue to the device by management software running in a trusted zone. The new configuration is parsed and verified by trusted firmware, which, then, creates isolated IO command queues on the acceleration device. These IO command queues can be directly mapped to a user application, VM, or other PCIe devices. In one embodiment, each IO command queue exposes only the compute resource assigned by the trusted firmware in the acceleration device.

公开(公告)号：US20240104045A1

公开(公告)日：2024-03-28

申请号：US18447180

申请日：2023-08-09

Applicant: Enfabrica Corporation

Inventor： Thomas Norrie ,  Frederic Vecoven ,  Kiran Seshadri ,  Shrijeet Mukherjee ,  Chetan Loke

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: A system for sharing peripheral component interconnect express (PCIe) devices across multiple host servers is disclosed. In some embodiments, a switch includes a plurality of hosts associated with a plurality of hierarchies, one or more endpoints associated with one or more of the plurality of hierarchies, and a switch communicatively connectable to the plurality of hosts and the one or more endpoints. The switch is configured to: receive a transaction layer packet (TLP); determine a policy group identifier based on parsing and processing the TLP; perform packet forward matching based on the policy group identifier and destination fields of the TLP; based on whether the TLP is communicated between the hosts and endpoints in different hierarchies of the plurality of hierarchies, determine whether to edit the TLP using one or more rewrite rules; and forward the TLP to an appropriate destination link.

公开(公告)号：US20240104035A1

公开(公告)日：2024-03-28

申请号：US18534037

申请日：2023-12-08

Applicant: SK hynix Inc.

Inventor： Yong Tae JEON ,  Ji Woon YANG ,  Dae Sik PARK

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: An SSD device comprises a first port linking up with a first host using a first link, a second port linking up with the first host or a second host using a second link, and a port mode controller controlling the first port and the second port to change an operating mode from a dual port mode, in which the first port and the second port operate independently of each other, to a single port mode, in which only the first port operates. The port mode controller controls the second port to reset the second link in a state where the first link is linked up.

公开(公告)号：US20240095205A1

公开(公告)日：2024-03-21

申请号：US17987904

申请日：2022-11-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Liran Liss ,  Aviad Shaul Yehezkel ,  Rabia Loulou ,  Oren Duer ,  Shahaf Shuler ,  Chenghuan Jia ,  Philip Browning Johnson ,  Gal Shalom ,  Omri Kahalon ,  Adi Merav Horowitz ,  Arpit Jain ,  Eliav Bar-Ilan ,  Prateek Srivastava

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4022 ,  G06F13/404

Abstract: A system includes a bus interface and circuitry. The bus interface is configured to communicate with an external device over a peripheral bus. The circuitry is configured to support a plurality of widgets that perform primitive operations used in implementing peripheral-bus devices, to receive a user-defined configuration, which specifies a user-defined peripheral-bus device as a configuration of one or more of the widgets, and to implement the user-defined peripheral-bus device toward the external device over the peripheral bus, in accordance with the user-defined configuration.

公开(公告)号：US11934334B2

公开(公告)日：2024-03-19

申请号：US17244182

申请日：2021-04-29

Applicant: Arm Limited

Inventor： Tushar P Ringe ,  Mark David Werkheiser ,  Jamshed Jalal ,  Sai Kumar Marri ,  Ashok Kumar Tummala ,  Rishabh Jain

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/4068 ,  G06F13/4027 ,  G06F2213/0026

Abstract: The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

公开(公告)号：US11928191B2

公开(公告)日：2024-03-12

申请号：US17145479

申请日：2021-01-11

Applicant: DELL PRODUCTS, LP

Inventor： Viswanath Ponnuru ,  Rama Rao Bisa ,  Chandrashekar Nelogal ,  Chandrasekhar Mugunda ,  Lee E. Ballard

IPC: G06F21/31 ,  G06F8/65 ,  G06F13/42 ,  G06F21/57 ,  G06F21/60

CPC classification number: G06F21/31 ,  G06F8/65 ,  G06F13/4221 ,  G06F13/4282 ,  G06F21/57 ,  G06F21/604 ,  G06F2213/0016 ,  G06F2213/0026

Abstract: An information handling system includes a device capable of sending and receiving security protocol and data model messages. A management controller with an authorization role as a designated leader is configured to verify authenticity of the device, discover authorization capabilities of the device, and set the authorization role of the device as a follower.