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    Interrupt emulation on network devices
    1.
    发明授权
    Interrupt emulation on network devices 有权

    公开(公告)号：US12174765B2

    公开(公告)日：2024-12-24

    申请号：US17707555

    申请日：2022-03-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Liran Liss ,  Rabia Loulou ,  Aviad Yehezkel

    IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

    Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

    Data processing unit with transparent root complex
    3.
    发明公开
    Data processing unit with transparent root complex 审中-公开

    公开(公告)号：US20240143526A1

    公开(公告)日：2024-05-02

    申请号：US17976909

    申请日：2022-10-31

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

    IPC: G06F13/28 ,  G06F13/42

    CPC classification number: G06F13/28 ,  G06F13/4221

    Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

    LINK AGGREGATION IN INFINIBAND NETWORKS
    4.
    发明公开
    LINK AGGREGATION IN INFINIBAND NETWORKS 审中-公开

    公开(公告)号：US20240259298A1

    公开(公告)日：2024-08-01

    申请号：US18162174

    申请日：2023-01-31

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Adi Horowitz ,  Omri Kahalon ,  Gal Shalom ,  Rabia Loulou ,  Aviad Yehezkel ,  Matty Kadosh

    IPC: H04L45/24 ,  H04L61/103

    CPC classification number: H04L45/245 ,  H04L61/103 ,  H04L2101/668

    Abstract: Systems and methods herein are for one or more processing units of a subnet manger (SM) to communicate configuration information with at least one subnet management agent (SMA) that is associated with at least one switch and with a host machine, the configuration information to enable the at least one switch to configure a forwarding table based in part on a mapping of at least one virtual network address to physical network addresses of two or more physical ports of the host machine, and the configuration information to enable the host machine to communicate with other host machines using the at least one switch and the at least one virtual network address.

    Data processing unit with transparent root complex
    8.
    发明授权
    Data processing unit with transparent root complex 有权

    公开(公告)号：US12117948B2

    公开(公告)日：2024-10-15

    申请号：US17976909

    申请日：2022-10-31

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

    IPC: G06F13/28 ,  G06F13/42

    CPC classification number: G06F13/28 ,  G06F13/4221

    Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

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