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公开(公告)号：US10776272B2
公开(公告)日：2020-09-15
申请号：US15058262
申请日：2016-03-02
发明人： Idan Burstein , Diego Crupnicoff , Shlomo Raikin , Michael Kagan
IPC分类号： G06F12/0831 , G06F3/06 , G06F12/128 , G06F13/28 , G06F13/42 , G06F15/173 , G06F12/0804
摘要： A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.
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公开(公告)号：US10430374B2
公开(公告)日：2019-10-01
申请号：US15196088
申请日：2016-06-29
发明人： Adi Menachem , Ariel Shahar , Noam Bloch , Diego Crupnicoff , Michael Kagan
IPC分类号： G06F15/173 , H04L29/06 , G06F13/28 , H04L1/16 , H04L1/18
摘要： A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.
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公开(公告)号：US20170063613A1
公开(公告)日：2017-03-02
申请号：US15250953
申请日：2016-08-30
发明人： Gil Bloch , Diego Crupnicoff , Benny Koren , Oded Wertheim , Lion Levi , Richard Graham , Michael Kagan
CPC分类号： H04L12/185 , H04L12/44 , H04L41/12
摘要： A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.
摘要翻译： 数据网络中的交换机被配置为中介网元之间的数据交换。 该装置还包括处理器，其将网络元件组织成具有根节点网络元件的分层树，顶点节点网络元素包括叶节点网络元素的子节点网络元素。 叶节点网元是始发聚合数据，并将聚合数据发送到相应的父顶点节点网元。 顶点节点网络元素组合来自至少一部分子节点网元的聚合数据，并将组合聚合数据从顶点节点网元发送到父顶点节点网元。 根节点网元可用于启动对聚合数据的简化操作。
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公开(公告)号：US08949486B1
公开(公告)日：2015-02-03
申请号：US13943809
申请日：2013-07-17
发明人： Michael Kagan , Diego Crupnicoff
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： An interface device includes a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device and a second proxy interface configured to carry out second DMA transactions initiated by a storage drive. A buffer memory is coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions. Control logic is configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer between the I/O device and the storage drive.
摘要翻译： 接口设备包括被配置为执行由输入/输出（I / O）设备发起的第一直接存储器访问（DMA）事务的第一代理接口和被配置为执行由存储驱动器发起的第二DMA事务的第二代理接口。 缓冲存储器耦合在第一和第二代理接口之间并被配置为临时保存在第一和第二DMA事务中传送的数据。 控制逻辑被配置为响应于第一DMA事务来调用第二DMA事务，以便使数据通过I / O设备和存储驱动器之间的缓冲器传送。
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公开(公告)号：US11765237B1
公开(公告)日：2023-09-19
申请号：US17724540
申请日：2022-04-20
发明人： Liran Liss , Yamin Friedman , Michael Kagan , Diego Crupnicoff , Idan Burstein , Matty Kadosh , Tzah Oved , Dror Goldenberg , Ron Yuval Efraim , Alexander Eli Rosenbaum , Aviad Yehezkel , Rabia Loulou
IPC分类号： H04L67/141 , H04L67/146 , G06F15/173 , H04L69/16 , H04L9/08
CPC分类号： H04L67/141 , G06F15/17331 , H04L9/0825 , H04L67/146 , H04L69/161
摘要： Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.
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公开(公告)号：US10284383B2
公开(公告)日：2019-05-07
申请号：US15250953
申请日：2016-08-30
发明人： Gil Bloch , Diego Crupnicoff , Benny Koren , Oded Wertheim , Lion Levi , Richard Graham , Michael Kagan
摘要： A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements, and child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.
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公开(公告)号：US20150195204A1
公开(公告)日：2015-07-09
申请号：US14662259
申请日：2015-03-19
发明人： Zachy Haramaty , Eitan Zahavi , Freddy Gabbay , Diego Crupnicoff , Amiad Marelli , Gil Bloch
IPC分类号： H04L12/803 , H04L12/703
CPC分类号： H04L47/122 , H04L45/28
摘要： A method includes receiving in a network switch of a communication network communication traffic that originates from a source node and arrives over a route through the communication network traversing one or more preceding network switches, for forwarding to a destination node. In response to detecting in the network switch a compromised ability to forward the communication traffic to the destination node, a notification is sent to the preceding network switches. The notification is to be consumed by the preceding network switches and requests the preceding network switches to modify the route so as not to traverse the network switch.
摘要翻译： 一种方法包括在网络交换机中接收来自源节点的通信网络通信业务，并通过穿过一个或多个先前网络交换机的通信网络到达路由，以转发到目的地节点。 响应于在网络交换机中检测到将通信业务转发到目的地节点的能力受损，向前一个网络交换机发送通知。 该通知将由上述网络交换机使用，并请求上述网络交换机修改路由，以免穿越网络交换机。
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公开(公告)号：US09014006B2
公开(公告)日：2015-04-21
申请号：US13754921
申请日：2013-01-31
发明人： Zachy Haramaty , Eitan Zahavi , Freddy Gabbay , Diego Crupnicoff , Amiad Marelli , Gil Bloch
IPC分类号： H04L12/26 , H04L12/803
CPC分类号： H04L47/122
摘要： A method includes receiving in a network switch of a communication network communication traffic that originates from a source node and arrives over a route through the communication network traversing one or more preceding network switches, for forwarding to a destination node. In response to detecting in the network switch a compromised ability to forward the communication traffic to the destination node, a notification is sent to the preceding network switches. The notification is to be consumed by the preceding network switches and requests the preceding network switches to modify the route so as not to traverse the network switch.
摘要翻译： 一种方法包括在网络交换机中接收来自源节点的通信网络通信业务，并通过穿过一个或多个先前网络交换机的通信网络到达路由，以转发到目的地节点。 响应于在网络交换机中检测到将通信业务转发到目的地节点的能力受损，向前一个网络交换机发送通知。 该通知将由上述网络交换机使用，并请求上述网络交换机修改路由，以免穿越网络交换机。
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公开(公告)号：US20150026368A1
公开(公告)日：2015-01-22
申请号：US13943809
申请日：2013-07-17
发明人： Michael Kagan , Diego Crupnicoff
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： An interface device includes a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device and a second proxy interface configured to carry out second DMA transactions initiated by a storage drive. A buffer memory is coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions. Control logic is configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer between the I/O device and the storage drive.
摘要翻译： 接口设备包括被配置为执行由输入/输出（I / O）设备发起的第一直接存储器访问（DMA）事务的第一代理接口和被配置为执行由存储驱动器发起的第二DMA事务的第二代理接口。 缓冲存储器耦合在第一和第二代理接口之间并被配置为临时保存在第一和第二DMA事务中传送的数据。 控制逻辑被配置为响应于第一DMA事务来调用第二DMA事务，以便使数据通过I / O设备和存储驱动器之间的缓冲器传送。
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公开(公告)号：US20190034381A1
公开(公告)日：2019-01-31
申请号：US15659876
申请日：2017-07-26
发明人： Idan Burstein , Diego Crupnicoff
IPC分类号： G06F15/167 , G06F15/173 , H04L29/06
CPC分类号： G06F15/167 , G06F15/17331 , H04L67/1097 , H04L67/42
摘要： Communication apparatus includes a host interface, configured to be coupled to a host processor having a host memory, and a network interface, which is configured to receive over a network from a sending node data packets conveying operations for execution in a sequential order on a predefined queue pair (QP), including at least a first packet conveying a posted write operation and a second packet conveying a non-posted write operation. Packet processing circuitry is configured to execute the posted write operation in accordance with the sequential order so as to write first data to the host memory prior to the execution of any subsequent operations in the sequential order, and to execute the non-posted write operation so as to write second data to the host memory while allowing one or more of the subsequent operations in the sequential order to be executed prior to completion of writing the second data.
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