公开(公告)号：US08999793B2

公开(公告)日：2015-04-07

申请号：US14306250

申请日：2014-06-17

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

Abstract translation: 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从内向外减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

公开(公告)号：US20150061042A1

公开(公告)日：2015-03-05

申请号：US14016234

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Nien-Ting Ho ,  Chien-Hao Chen ,  Ching-Yun Chang ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chi-Yuan Sun ,  Chi-Mao Hsu

IPC: H01L29/49 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/285

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.

Abstract translation: 提供了金属栅极结构。 金属栅极结构包括半导体衬底，栅极电介质层，多层P型功函数层和导电金属层。 栅极电介质层设置在半导体衬底上。 多层P型功函数层设置在栅极电介质层上，多层P型功函数层至少包含结晶P型功函数层和至少一非晶P型功函数层 层。 此外，导电性金属层设置在多层P型功函数层上。

公开(公告)号：US20250013157A1

公开(公告)日：2025-01-09

申请号：US18447324

申请日：2023-08-10

Applicant: United Microelectronics Corp.

Inventor： Chun-Yi Chang ,  Chien-Hao Chen

IPC: G03F7/00

Abstract: Provided are a manufacturing method of an overlay mark and an overlay measurement method. The manufacturing method includes the following steps. A first stitching overlay mark structure having a plurality of first patterns is formed on a first layer. A second layer is formed on the first layer. A second stitching overlay mark structure having a plurality of second patterns is formed on the second layer. The second stitching overlay mark structure is located above the first stitching overlay mark structure, and from the top view on the second layer, the second patterns and the first patterns are alternately arranged.

公开(公告)号：US20240411221A1

公开(公告)日：2024-12-12

申请号：US18346279

申请日：2023-07-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Yi Chang ,  Chien-Hao Chen

IPC: G03F1/42 ,  G03F1/44 ,  G03F1/68 ,  G03F7/00

Abstract: A photomask set including a first photomask and a second photomask is provided. The first photomask includes a first pattern. The first pattern includes a first main portion and a first stitching portion connected to each other. The first stitching portion includes a first matching portion and a first overlapping portion connected to each other. The second photomask includes a second pattern. The second pattern includes a second main portion and a second stitching portion connected to each other. The second stitching portion includes a second matching portion and a second overlapping portion connected to each other. After the first photomask is aligned with the second photomask, the first matching portion matches the second matching portion, the first overlapping portion overlaps the second pattern, and the second overlapping portion overlaps the first pattern.

公开(公告)号：US10707092B1

公开(公告)日：2020-07-07

申请号：US16245163

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hung Wang ,  En-Chiuan Liou ,  Chien-Hao Chen ,  Jhao-Hao Lee ,  Sho-Shen Lee ,  Chih-Yu Chiang

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L27/108

Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

公开(公告)号：US10170623B2

公开(公告)日：2019-01-01

申请号：US15796874

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Tang-Chun Weng ,  Chien-Hao Chen

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.

公开(公告)号：US10079185B1

公开(公告)日：2018-09-18

申请号：US15630966

申请日：2017-06-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Hao Chen ,  Chien-Wei Huang ,  Chia-Hung Wang ,  Sho-Shen Lee

IPC: H01L21/66 ,  G01R31/26

Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.

公开(公告)号：US20170207093A1

公开(公告)日：2017-07-20

申请号：US15479292

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

公开(公告)号：US20150279957A1

公开(公告)日：2015-10-01

申请号：US14230223

申请日：2014-03-31

Applicant: United Microelectronics Corp.

Inventor： Yu-Ping Wang ,  Jyh-Shyang Jenq ,  Yu-Hsiang Lin ,  Hsuan-Hsu Chen ,  Chien-Hao Chen ,  Yi-Han Ye

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括第一栅极结构，第二栅极结构和第二电介质间隔物。 彼此相邻的第一栅极结构和第二栅极结构中的每一个包括第一电介质间隔物。 第二电介质间隔物位于第一栅极结构的相对侧壁中的一个上，而不设置在第二栅极结构的电介质间隔物上。

公开(公告)号：US09076784B2

公开(公告)日：2015-07-07

申请号：US14454727

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun ,  Ya-Hsueh Hsieh ,  Tsun-Min Cheng

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构包括功函数金属层，（功函数）金属氧化物层和主电极。 功函数金属层位于基板上。 （功函数）金属氧化物层位于功函数金属层上。 主电极位于（功函数）金属氧化物层上。 还提供了形成所述半导体结构的半导体工艺。