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公开(公告)号：US10707213B2
公开(公告)日：2020-07-07
申请号：US16178521
申请日：2018-11-01
Inventor： Chia-Hung Wang , En-Chiuan Liou , Chien-Hao Chen , Sho-Shen Lee , Yi-Ting Chen , Jhao-Hao Lee
IPC: H01L21/311 , H01L27/108 , H01L21/027 , H01L21/033
Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
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公开(公告)号：US10453849B2
公开(公告)日：2019-10-22
申请号：US15936396
申请日：2018-03-26
Inventor： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC: H01L29/02 , H01L27/108 , G11C11/401
Abstract: The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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公开(公告)号：US10373915B1
公开(公告)日：2019-08-06
申请号：US16202104
申请日：2018-11-28
Inventor： Hsiao-Lin Hsu , En-Chiuan Liou , Yi-Ting Chen , Sho-Shen Lee
IPC: H01L23/544 , H01L21/66 , G01B11/27 , H01L21/8234
Abstract: A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.
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公开(公告)号：US09490217B1
公开(公告)日：2016-11-08
申请号：US14687912
申请日：2015-04-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Ching Lin , En-Chiuan Liou , Chia-Hung Wang , Sho-Shen Lee
IPC: H01L23/544 , H01L21/68 , H01L29/78
CPC classification number: H01L29/785 , G03F7/70633 , G03F7/70683
Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.
Abstract translation: 在本发明中提供了用于确定在衬底上方与两个连续层形成的两个单独产生的图案之间的对准的覆盖标记，其中衬底和覆盖标记都包括具有不同取向的周期性结构的至少两个图案区域，以及 覆盖标记的周期性结构与衬底的周期性结构正交地重叠。
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公开(公告)号：US10707092B1
公开(公告)日：2020-07-07
申请号：US16245163
申请日：2019-01-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Hung Wang , En-Chiuan Liou , Chien-Hao Chen , Jhao-Hao Lee , Sho-Shen Lee , Chih-Yu Chiang
IPC: H01L21/00 , H01L21/311 , H01L21/768 , H01L21/033 , H01L27/108
Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.
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Patent Agency Ranking
公开(公告)号：US10079185B1
公开(公告)日：2018-09-18
申请号：US15630966
申请日：2017-06-23
Inventor： Chien-Hao Chen , Chien-Wei Huang , Chia-Hung Wang , Sho-Shen Lee
Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
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公开(公告)号：US09304389B2
公开(公告)日：2016-04-05
申请号：US14067986
申请日：2013-10-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang
Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
Abstract translation: 提供包括第一不透明图案和第二不透明图案的光掩模。 第一不透明图案分布在光掩模中限定的第一平面中，而第二不透明图案设置在第一不透明图案之上并与第一不透明图案隔开。 换句话说，第一不透明图案和第二不透明图案不分布在同一平面中。
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公开(公告)号：US20150118602A1
公开(公告)日：2015-04-30
申请号：US14067986
申请日：2013-10-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang
Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
Abstract translation: 提供包括第一不透明图案和第二不透明图案的光掩模。 第一不透明图案分布在光掩模中限定的第一平面中，而第二不透明图案设置在第一不透明图案之上并与第一不透明图案间隔开。 换句话说，第一不透明图案和第二不透明图案不分布在同一平面中。
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公开(公告)号：US08954919B1
公开(公告)日：2015-02-10
申请号：US14069391
申请日：2013-11-01
Applicant: United Microelectronics Corp.
Inventor： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang , Yu-Chin Huang
IPC: G06F17/50
CPC classification number: G03F1/70
Abstract: A calculation method for generating a layout pattern in a photomask includes at least the following steps. A two-dimensional design layout including several geometric patterns distributed in a plane is provided to a computer system. The computer system is used to mark portions of the geometric patterns and generate at least one marked geometric pattern and at least one non-marked geometric pattern. The marked geometric pattern is then simulated and corrected by the computer system so as to generate a 3-D design layout. Through the simulation and correction, the marked geometric pattern and the non-marked geometric pattern are arranged alternately along an axis orthogonal to the plane. The 3-D design layout is outputted to a mask-making system afterwards.
Abstract translation: 用于生成光掩模中的布局图案的计算方法至少包括以下步骤。 将包括分布在平面中的几个几何图案的二维设计布局提供给计算机系统。 计算机系统用于标记几何图案的部分并且生成至少一个标记的几何图案和至少一个未标记的几何图案。 然后通过计算机系统模拟和校正标记的几何图案，以生成3维设计布局。 通过模拟和校正，标记的几何图案和未标记的几何图案沿着与平面正交的轴线交替布置。 3-D设计布局随后输出到制版系统。
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公开(公告)号：US20200013783A1
公开(公告)日：2020-01-09
申请号：US16571202
申请日：2019-09-16
Inventor： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC: H01L27/108 , G11C11/401
Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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