公开(公告)号：US20080092376A1

公开(公告)日：2008-04-24

申请号：US11552368

申请日：2006-10-24

申请人： Jaroslaw A. Magera ,  Gregory J. Dunn ,  Jovica Savic

发明人： Jaroslaw A. Magera ,  Gregory J. Dunn ,  Jovica Savic

IPC分类号： H01L21/00

CPC分类号： H05K3/20 ,  H05K1/167 ,  H05K3/06 ,  H05K3/205 ,  H05K3/244 ,  H05K2201/0361 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

摘要： Fabricating (100, 1300) a printed circuit board includes fabricating patterned conductive traces (305, 310, 1410, 1415) onto a foil, laminating the patterned conductive traces to a printed circuit board substrate (405, 1505) by pressing on the foil, such that the conductive traces are pressed into a dielectric layer of the printed circuit board, and removing the foil to expose a co-planar surface of conductive trace surfaces and dielectric surfaces. Removal may be done by peeling (125) and/or etching (130, 1315).

摘要翻译： 制造（100,1300）印刷电路板包括在箔上制造图案化的导电迹线（305,310,1410,1415），通过压在箔上将图案化的导电迹线层压到印刷电路板衬底（405,1505）上， 使得导电迹线被压入印刷电路板的电介质层，并且去除箔以暴露导电迹线表面和电介质表面的共面表面。 可以通过剥离（125）和/或蚀刻（130,1315）进行去除。

公开(公告)号：US07361568B2

公开(公告)日：2008-04-22

申请号：US11316087

申请日：2005-12-21

申请人： Gregory J. Dunn ,  Remy J. Chelini ,  Robert T. Croswell ,  Philip M. Lessner ,  Michael D. Prevallet ,  John D. Prymak

发明人： Gregory J. Dunn ,  Remy J. Chelini ,  Robert T. Croswell ,  Philip M. Lessner ,  Michael D. Prevallet ,  John D. Prymak

IPC分类号： H01L21/20 ,  H01L29/00 ,  H01L23/48 ,  H01G4/005

CPC分类号： H01G9/045 ,  H01G9/0032 ,  H01G9/055 ,  H01G9/15 ,  H05K1/162 ,  H05K3/383 ,  H05K3/429 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0315

摘要： Embedded capacitors comprise a bimetal foil (500) that includes a first copper layer (205) and an aluminum layer (210) on the first copper layer. The aluminum layer has a smooth side adjacent the first copper layer and a high surface area textured side (215) opposite the first copper layer. The bimetal foil further includes an aluminum oxide layer (305) on the high surface area textured side of the aluminum layer, a conductive polymerlayer (420) on the aluminum oxide layer, and a second copper layer (535) overlying the aluminum oxide layer. The bimetal foil may be embedded in a circuit board (700) to form high value embedded capacitors.

摘要翻译： 嵌入式电容器包括在第一铜层上包括第一铜层（205）和铝层（210）的双金属箔（500）。 铝层具有邻近第一铜层的平滑侧面和与第一铜层相对的高表面积纹理化侧面（215）。 双金属箔还包括在铝层的高表面积纹理化侧的氧化铝层（305），氧化铝层上的导电聚合物层（420）和覆盖在氧化铝层上的第二铜层（535）。 双金属箔可以嵌入在电路板（700）中以形成高价值的嵌入式电容器。

公开(公告)号：US07241510B2

公开(公告)日：2007-07-10

申请号：US11139056

申请日：2005-05-27

申请人： Gregory J. Dunn ,  Remy J. Chelini ,  Timothy B. Dean

发明人： Gregory J. Dunn ,  Remy J. Chelini ,  Timothy B. Dean

IPC分类号： B32B15/00

CPC分类号： H05K3/025 ,  B32B7/06 ,  B32B9/00 ,  B32B9/041 ,  B32B15/00 ,  B32B15/043 ,  B32B15/20 ,  B32B2264/102 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/54 ,  B32B2307/546 ,  B32B2307/714 ,  B32B2457/08 ,  H05K3/384 ,  H05K2201/0175 ,  H05K2203/0264 ,  Y10T428/12493 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/24917 ,  Y10T428/24926

摘要： In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic high temperature release structure (215) that comprises a co-deposited layer (250) and a metal oxide layer (260). The co-deposited layer comprises an admixture of nickel and one or more of boron, phosphorus, and chromium. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

摘要翻译： 在一个实施例中，可剥离电路板箔（200）具有通过包含共沉积层（250）的无机高温释放结构（215）结合的金属支撑层（205）和导电金属箔层（210） 和金属氧化物层（260）。 共沉积层包含镍和硼，磷和铬中的一种或多种的混合物。 在第二实施例中，可剥离印刷电路箔（200）具有设置在金属箔层上的结晶化电介质氧化物层（405）和设置在结晶化电介质氧化物层上的电极层（415），形成介电剥离电路板箔 （400），其可以粘附到柔性或刚性电路板的层上，之后金属支撑层可以被剥离，留下包括金属箔层，结晶的电介质氧化物层和电极层的电容结构。

公开(公告)号：US07079373B2

公开(公告)日：2006-07-18

申请号：US10837461

申请日：2004-04-30

申请人： Gregory J. Dunn ,  Jeffrey M. Petsinger ,  Jovica Savic

发明人： Gregory J. Dunn ,  Jeffrey M. Petsinger ,  Jovica Savic

IPC分类号： H01G4/06 ,  H05K1/11

CPC分类号： H05K3/0023 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/064 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0571

摘要： A dielectric sheet (500, 600, 1621) includes a photodielectric support layer (505, 1630) that may be glass reinforced and a dielectric laminate (510, 605). The dielectric laminate includes first and second metal foil layers (415, 660; 210, 665, 1605, 1610), and a dielectric layer (405, 655, 1620) disposed between the first and second metal foil layers. The first metal foil layer is adhered to the photodielectric support layer. In a printed circuit and patch antenna that includes the dielectric sheet, the first metal layer is patterned by removal of metal according to a circuit pattern and the photodielectric support layer is patterned by removal of dielectric material according to the circuit pattern.

摘要翻译： 电介质片（500,600,1621）包括可以被玻璃增强的光电介质支撑层（505,1630）和介电层压板（510,605）。 介电层压板包括设置在第一和第二金属箔层之间的第一和第二金属箔层（415,660; 210,665,1605,1610）和介电层（405,655,1620）。 第一金属箔层粘附到光致介电支撑层上。 在包括电介质片的印刷电路和贴片天线中，通过根据电路图案去除金属来对第一金属层进行构图，并且通过根据电路图案去除介电材料来对光致介电支撑层进行图案化。

公开(公告)号：US07078796B2

公开(公告)日：2006-07-18

申请号：US10610745

申请日：2003-07-01

申请人： Gregory J. Dunn ,  Owen R. Fay ,  Timothy B. Dean ,  Terance Blake ,  Remy J. Chelini ,  William H. Lytle ,  George A. Strumberger

发明人： Gregory J. Dunn ,  Owen R. Fay ,  Timothy B. Dean ,  Terance Blake ,  Remy J. Chelini ,  William H. Lytle ,  George A. Strumberger

IPC分类号： H01L23/48

CPC分类号： H01L24/12 ,  G01L19/0069 ,  G01L19/147 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： The invention provides an integrated device with corrosion-resistant capped copper bond pads. The capped copper bond pads include at least one copper bond pad on a semiconductor substrate. An activation layer comprising one of immersion palladium, electroless cobalt, or immersion ruthernium is disposed on the copper bond pad. A first intermediate layer of electroless nickel-boron alloy is disposed on the activation layer. A second intermediate layer comprising one of electroless nickel or electroless palladium is disposed on the first intermediate layer, and an immersion gold layer is disposed on the second intermediate layer. A capped copper bond pad and a method of forming the capped copper bond pads are also disclosed.

摘要翻译： 本发明提供了一种具有耐腐蚀的封盖铜焊盘的集成器件。 封装的铜键合焊盘包括半导体衬底上的至少一个铜焊盘。 包含浸渍钯，无电解钴或浸渍铯中的一种的活化层设置在铜键合焊盘上。 化学镀镍 - 硼合金的第一中间层设置在活化层上。 在第一中间层上设置包含非电解镍或无电解钯中的一种的第二中间层，在第二中间层上设置浸金层。 还公开了封盖铜键合焊盘和形成封盖铜键合焊盘的方法。

公开(公告)号：US07056800B2

公开(公告)日：2006-06-06

申请号：US10736327

申请日：2003-12-15

申请人： Robert T. Croswell ,  Gregory J. Dunn ,  Robert B. Lempkowski ,  Aroon V. Tungare ,  Jovica Savic

发明人： Robert T. Croswell ,  Gregory J. Dunn ,  Robert B. Lempkowski ,  Aroon V. Tungare ,  Jovica Savic

IPC分类号： H01L21/20 ,  H01G4/00

CPC分类号： H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

摘要： One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

摘要翻译： 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。 结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。 多个电容器的材料和厚度相同。 结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

公开(公告)号：US06349456B1

公开(公告)日：2002-02-26

申请号：US09224338

申请日：1998-12-31

申请人： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler ,  Min-Xian Zhang ,  Everett Simons

发明人： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler ,  Min-Xian Zhang ,  Everett Simons

IPC分类号： H01G700

CPC分类号： H05K1/162 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/09509 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

摘要翻译： 一种用于制造具有对准的导电区域和具有期望的处理和尺寸特性的电介质区域的微电子组件的方法。 本发明对于制造集成电容器特别有用，具有通过本发明实现的期望的处理和尺寸特性，为电容器产生可预测的电特性。 该方法通常需要提供具有第一导电层的衬底，在第一导电层上形成电介质层，然后在电介质层上形成第二导电层。 然后去除第二导电层的第一区域以暴露介电层的第一区域，该第一区域又被去除以暴露也被去除的第一导电层的第一区域。 从该工艺中，通过使用上覆层作为掩模，导电和介电层的第一区域各自被去除，使得这些层的剩余的第二区域是共延伸的。

公开(公告)号：US06194990B1

公开(公告)日：2001-02-27

申请号：US09268956

申请日：1999-03-16

申请人： Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

发明人： Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

IPC分类号： H01C101

CPC分类号： H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

摘要： A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

摘要翻译： 适用于多层印刷电路板（12）的薄膜金属电阻（44）及其制造方法。 电阻器（44）通常具有多层结构，其中电阻器（44）的各个层（34,38）彼此自对准，使得产生负的互感，其几乎抵消了自感 的每个电阻层（34,38）。 结果，电阻器（44）具有非常低的净寄生电感。 此外，电阻器（44）的多层结构减小了容纳电阻器（44）所需的电路板（12）的面积，结果减少了与其他层上的其它电路元件的寄生相互作用的问题 电路板（12）。

公开(公告)号：US5994997A

公开(公告)日：1999-11-30

申请号：US976467

申请日：1997-11-24

申请人： Vernon L. Brown ,  Gregory J. Dunn ,  Lawrence E. Lach

发明人： Vernon L. Brown ,  Gregory J. Dunn ,  Lawrence E. Lach

IPC分类号： H01C1/012 ,  H01C1/148 ,  H01C1/16 ,  H01C17/28 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/46

CPC分类号： H05K1/167 ,  H01C1/012 ,  H01C1/148 ,  H01C1/16 ,  H01C17/281 ,  H05K1/095 ,  H05K1/116 ,  H05K2201/09509 ,  H05K2203/1453 ,  H05K3/0023 ,  H05K3/4644 ,  Y10T29/49099 ,  Y10T29/49101

摘要： A thick-film resistor and a process for forming the resistor to have accurate dimensions, thereby yielding a precise resistance value. The resistor generally includes an electrically resistive layer and a pair of terminals, a first of which is surrounded by the second terminal, so as to form a region therebetween that surrounds the first terminal and separates the first and second terminals. The terminals are preferably concentric, with the second terminal and the region therebetween being annular-shaped. The resistive layer electrically connects the first and second terminals to complete the resistor. Each of the terminals has a surface that is substantially parallel to an upper and/or lower surface of the resistive layer and contacts the resistive layer. The surfaces of the terminals may be embedded in the resistive layer by printing the resistive material over the terminals, or may contact the upper or lower surface of the resistive layer by locating the terminals above or below the resistive layer. In each of these embodiments, the terminals are not limited to having edge-to-edge contact with the resistive layer, such that the interfacial resistance therebetween is minimized.

公开(公告)号：US08652920B2

公开(公告)日：2014-02-18

申请号：US13409424

申请日：2012-03-01

申请人： John D. Prymak ,  Chris Stolarski ,  Alethla Melody ,  Antony P. Chacko ,  Gregory J. Dunn

发明人： John D. Prymak ,  Chris Stolarski ,  Alethla Melody ,  Antony P. Chacko ,  Gregory J. Dunn

IPC分类号： H01L27/108 ,  H01G4/005

CPC分类号： H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

摘要翻译： 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。