公开(公告)号：US20150001592A1

公开(公告)日：2015-01-01

申请号：US13930161

申请日：2013-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC: H01L23/525 ,  H01L21/306

CPC classification number: H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

Abstract translation: 提供具有金属保险丝的半导体器件。 金属熔断器连接电子部件（例如，晶体管）和接地的现有虚拟特征。 金属保险丝的保护可以设计为在金属化形成工艺开始时开始。 接地的虚拟特征提供了在线路过程的整个后端期间等离子体对地面充电的路径。 金属保险丝是与二极管相反的过程电平保护，这是电路级保护。 作为工艺级保护，金属保险丝保护随后形成的电路。 此外，除了已经实现的内部虚拟图案之外，芯片中的金属熔断器不需要额外的有源区域。

公开(公告)号：US20140374832A1

公开(公告)日：2014-12-25

申请号：US13924731

申请日：2013-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gwo-Chyuan Kuoh ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien ,  Yen-Ming Peng

IPC: H01L29/78 ,  H01L21/768

CPC classification number: H01L29/7843 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/823871 ,  H01L23/00 ,  H01L29/7842 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.

Abstract translation: 本公开内容涉及具有一个或多个后端行（BEOL）选择应力膜的集成芯片，其应用提高BEOL选择应力膜下面的半导体器件的性能的应力，以及相关联的方法 形成。 在一些实施例中，集成芯片具有带有一个或多个具有第一器件类型的半导体器件的半导体衬底。 应力传递元件位于一个或多个半导体器件上方的位置处的后端行堆叠中。 选择应力膜位于应力传递元件上方。 选择应力膜在应力转移元件上引起应力，其中应力具有取决于一个或多个半导体器件的第一器件类型的压缩或拉伸状态。 应力作用在一个或多个半导体器件上以提高它们的性能。

公开(公告)号：US12148792B2

公开(公告)日：2024-11-19

申请号：US18358399

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US11362089B2

公开(公告)日：2022-06-14

申请号：US16730271

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Cheng-Wei Lian

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor structures and method for forming the same are provided. The method for manufacturing the semiconductor structure includes forming a first gate dielectric layer over a substrate and forming a first capping layer over the first gate dielectric layer. The method for manufacturing the semiconductor structure includes oxidizing the first capping layer to form a first capping oxide layer and forming a first work function metal layer over the first capping oxide layer. The method for manufacturing the semiconductor structure includes forming a first gate electrode layer over the first work function metal layer.

公开(公告)号：US11121217B2

公开(公告)日：2021-09-14

申请号：US16889511

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lung Chen ,  Kang-Min Kuo ,  Long-Jie Hong

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/36 ,  H01L21/033

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.

公开(公告)号：US11063039B2

公开(公告)日：2021-07-13

申请号：US16048744

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cong-Min Fang ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

公开(公告)号：US11056384B2

公开(公告)日：2021-07-06

申请号：US16678666

申请日：2019-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L23/485 ,  H01L21/8238 ,  H01L29/165 ,  H01L23/532

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US10727321B2

公开(公告)日：2020-07-28

申请号：US16668787

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung Chen ,  Kang-Min Kuo ,  Wen-Hsin Chan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure over a semiconductor substrate, and forming a mask layer covering the dummy fin structure. The method further includes irradiating the mask layer, so that the mask layer is divided into an unirradiated portion and an irradiated portion, and the irradiated portion is over the dummy fin structure. The method also includes removing a top portion of the irradiated portion and a top portion of the dummy fin structure by a first etching operation, such that the dummy fin structure has a convex top surface after the first etching operation. The method includes removing a middle portion of the dummy fin structure by a second etching operation, such that the dummy fin structure has a concave top surface after the second etching operation.

公开(公告)号：US10043802B2

公开(公告)日：2018-08-07

申请号：US14689859

申请日：2015-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Cheng-Wei Lian

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8238

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The gate structure includes a gate dielectric layer formed over the substrate and a capping layer formed over the gate dielectric layer. The gate structure further includes a capping oxide layer formed over the capping layer and a work function metal layer formed over the capping oxide layer. The gate structure further includes a gate electrode layer formed over the work function metal layer.

公开(公告)号：US10008568B2

公开(公告)日：2018-06-26

申请号：US14704324

申请日：2015-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Lung Chen ,  Kang-Min Kuo ,  Wen-Hsin Chan

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate. The semiconductor device structure also includes a source/drain structure over the semiconductor substrate, and the source/drain structure includes a dopant. The semiconductor device structure further includes a channel region under the gate stack. In addition, the semiconductor device structure includes a semiconductor layer surrounding the source/drain structure. The semiconductor layer is configured to prevent the dopant from entering the channel region.