公开(公告)号：US09991123B2

公开(公告)日：2018-06-05

申请号：US15584650

申请日：2017-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mei-Chun Chen ,  Ching-Chen Hao ,  Wen-Hsin Chan ,  Chao-Jui Wang

IPC: H01L23/48 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/485 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/408 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.

公开(公告)号：US09136340B2

公开(公告)日：2015-09-15

申请号：US13910610

申请日：2013-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mei-Chun Chen ,  Ching-Chen Hao ,  Wen-Hsin Chan ,  Chao-Jui Wang

IPC: H01L23/48 ,  H01L29/40 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/408 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括具有第一掺杂区和第二掺杂区的半导体衬底和形成在半导体衬底上的栅叠层。 半导体器件还包括形成在栅叠层的侧壁上的主间隔层。 半导体器件还包括形成在主间隔层和半导体衬底之间的保护层，并且保护层掺杂有四价元素。 此外，半导体器件包括形成在半导体衬底和栅极堆叠上的绝缘层和形成在绝缘层中的接触。 接触件具有接触第一掺杂区域的第一部分，并且具有接触第二掺杂区域的第二部分。 第一区域比第二部分更深地延伸到半导体衬底中。

公开(公告)号：US10147805B2

公开(公告)日：2018-12-04

申请号：US14815349

申请日：2015-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Lung Chen ,  Kang-Min Kuo ,  Wen-Hsin Chan

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.

公开(公告)号：US09647087B2

公开(公告)日：2017-05-09

申请号：US14843720

申请日：2015-09-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mei-Chun Chen ,  Ching-Chen Hao ,  Wen-Hsin Chan ,  Chao-Jui Wang

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/51

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/408 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening.

公开(公告)号：US11848367B2

公开(公告)日：2023-12-19

申请号：US17327111

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Wen Hsieh ,  Wen-Hsin Chan

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/42372 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for manufacturing a semiconductor device is provided. The method includes etching a dummy gate to form a gate trench to expose a channel portion of a first fin and a first isolation structure; depositing a gate dielectric layer and first and second work function layers, wherein the second work function layer has a first portion directly over the channel portion of the first fin and a second portion directly over the first isolation structure; etching the second portion of the second work function layer, wherein the first portion of the second work function layer remains; depositing a third work function layer over and in contact with the first portion of the second work function layer and the first work function layer; and filling the gate trench with a gate metal.

公开(公告)号：US11081571B2

公开(公告)日：2021-08-03

申请号：US16928942

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung Chen ,  Kang-Min Kuo ,  Wen-Hsin Chan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation.

公开(公告)号：US11018234B2

公开(公告)日：2021-05-25

申请号：US16045796

申请日：2018-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Wen Hsieh ,  Wen-Hsin Chan

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate and a gate structure. The semiconductor substrate includes a first semiconductor fin and a second semiconductor fin. The gate structure includes a work function metal structure crossing over the first semiconductor fin and the second semiconductor fin. The work function metal structure comprises a first portion over a portion of the first semiconductor fin, a second portion over a portion of the second semiconductor fin, and a third portion connecting the first portion to the second portion, wherein a thickness of the third portion is smaller than a thickness of the second portion and greater than a thickness of the first portion along an extension direction of the second semiconductor fin.

公开(公告)号：US12283595B2

公开(公告)日：2025-04-22

申请号：US17655321

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Chen-Bin Lin ,  Wen-Hsin Chan

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

公开(公告)号：US20230154922A1

公开(公告)日：2023-05-18

申请号：US17655321

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Chen-Bin Lin ,  Wen-Hsin Chan

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0924 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

公开(公告)号：US10727321B2

公开(公告)日：2020-07-28

申请号：US16668787

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung Chen ,  Kang-Min Kuo ,  Wen-Hsin Chan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure over a semiconductor substrate, and forming a mask layer covering the dummy fin structure. The method further includes irradiating the mask layer, so that the mask layer is divided into an unirradiated portion and an irradiated portion, and the irradiated portion is over the dummy fin structure. The method also includes removing a top portion of the irradiated portion and a top portion of the dummy fin structure by a first etching operation, such that the dummy fin structure has a convex top surface after the first etching operation. The method includes removing a middle portion of the dummy fin structure by a second etching operation, such that the dummy fin structure has a concave top surface after the second etching operation.