公开(公告)号：US20230154922A1

公开(公告)日：2023-05-18

申请号：US17655321

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Chen-Bin Lin ,  Wen-Hsin Chan

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0924 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.