公开(公告)号：US20250106048A1

公开(公告)日：2025-03-27

申请号：US18972272

申请日：2024-12-06

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Shih-Lien Linus Lu ,  Saman Adham ,  Yu-Der Chih

IPC: H04L9/32 ,  G06F3/06 ,  G06F12/06 ,  G06F21/75 ,  H04L9/08

Abstract: Disclosed herein is related to physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device. In one aspect, indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit. Each indirection process may include identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address. Through a number of indirection processes, hidden content stored by the OTP memory device can be obtained. In one approach, hashing can be applied to input bits to obtain an address of the OTP memory device to apply. In one approach, hashing can be applied to the hidden content stored by the OTP memory device to generate the key.

公开(公告)号：US12243592B2

公开(公告)日：2025-03-04

申请号：US18317665

申请日：2023-05-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih

IPC: G11C16/10 ,  G11C7/06 ,  G11C7/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C17/08

Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.

公开(公告)号：US12211579B2

公开(公告)日：2025-01-28

申请号：US18424164

申请日：2024-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/16 ,  G11C29/42

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

公开(公告)号：US12176063B2

公开(公告)日：2024-12-24

申请号：US17884650

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih ,  Jonathan Tsung-Yung Chang

IPC: G11C7/12 ,  G11C5/06 ,  G11C7/10 ,  G11C16/04 ,  G11C16/30

Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

公开(公告)号：US20240412785A1

公开(公告)日：2024-12-12

申请号：US18331570

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00

Abstract: A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.

公开(公告)号：US12165705B2

公开(公告)日：2024-12-10

申请号：US18362863

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-I Su ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Zheng-Jun Lin

IPC: G11C13/00

Abstract: A method of operating a memory circuit includes generating a first current in response to a first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.

公开(公告)号：US12073916B2

公开(公告)日：2024-08-27

申请号：US18138305

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih

IPC: G06F11/00 ,  G06F1/30 ,  G06F11/14 ,  G06F11/30 ,  G11C5/14 ,  G11C7/20 ,  G11C11/4072

CPC classification number: G11C7/20 ,  G06F1/30 ,  G06F11/1469 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/148 ,  G11C11/4072

Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.

公开(公告)号：US12041860B2

公开(公告)日：2024-07-16

申请号：US17581153

申请日：2022-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Wen-Zhang Lin ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Chrong-Jung Lin ,  Ya-Chin King ,  Cheng-Jun Lin ,  Wang-Yi Lee

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

公开(公告)号：US12009029B2

公开(公告)日：2024-06-11

申请号：US18185312

申请日：2023-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Meng-Fan Chang ,  May-Be Chen ,  Cheng-Xin Xue ,  Je-Syu Liu

IPC: G11C8/00 ,  G06F7/544 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14 ,  G11C13/00

CPC classification number: G11C13/004 ,  G06F7/5443 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/14 ,  G11C13/0069 ,  G11C2013/0054

Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

公开(公告)号：US11978518B2

公开(公告)日：2024-05-07

申请号：US17585031

申请日：2022-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chieh Chen ,  Cheng-Hsiung Kuo ,  Yu-Der Chih

IPC: G11C16/28 ,  G11C16/10 ,  H03K19/20

CPC classification number: G11C16/28 ,  G11C16/10 ,  H03K19/20

Abstract: A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.