公开(公告)号：US09941214B2

公开(公告)日：2018-04-10

申请号：US13968174

申请日：2013-08-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Yun Peng ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Kuang-Yuan Hsu

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L23/528

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.

公开(公告)号：US09647090B2

公开(公告)日：2017-05-09

申请号：US14586313

申请日：2014-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Cheng Wang ,  Chien-Feng Lin ,  Jeng-Yang Pan ,  Keng-Chu Lin

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/30 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3003 ,  H01L29/165

Abstract: The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin.

公开(公告)号：US20160260667A1

公开(公告)日：2016-09-08

申请号：US15157033

申请日：2016-05-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hui-Chun Yang ,  Mei-Ling Chen ,  Keng-Chu Lin ,  Joung-Wei Liou

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/28562 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.

Abstract translation: 公开了半导体器件，其制造方法以及形成其导电特征的方法。 半导体器件包括设置在工件上方的绝缘材料层。 绝缘材料层包括含有约13％或更多碳（C）的含硅材料。 导电特征设置在绝缘材料层内。 导电特征包括设置在其顶表面上的覆盖层。

公开(公告)号：US08940643B2

公开(公告)日：2015-01-27

申请号：US13971600

申请日：2013-08-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chi Ko ,  Chih-Hao Chen ,  Keng-Chu Lin

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31105 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832

Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.

Abstract translation: 光刻图案的方法包括在材料层上形成第一蚀刻停止层，第二蚀刻停止层和硬掩模层。 通过在第二蚀刻停止层，第一蚀刻停止层和材料层之间存在材料梯度组成的方式来选择第一蚀刻停止层和第二蚀刻停止层的材料。 因此，在蚀刻工艺中实现第二蚀刻停止层，第一蚀刻停止层和材料层之间的梯度蚀刻速率，以在第二和第一蚀刻停止层内形成具有平滑和/或垂直侧壁的蚀刻图案，并且 材料层。

公开(公告)号：US20240170323A1

公开(公告)日：2024-05-23

申请号：US18427575

申请日：2024-01-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Ko-Feng Chen ,  Zheng-Yong Liang ,  Chen-Han Wang ,  De-Yang Chiou ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/31116 ,  H01L21/823481

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures

公开(公告)号：US11855215B2

公开(公告)日：2023-12-26

申请号：US17855992

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuen-Shin Liang ,  Pang-Yen Tsai ,  Keng-Chu Lin ,  Sung-Li Wang ,  Pinyen Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  B82Y40/00

CPC classification number: H01L29/785 ,  H01L29/0676 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7827 ,  B82Y40/00 ,  H01L2029/7858

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor nanostructure and a second semiconductor nanostructure stacked over a substrate. The semiconductor device structure also includes a first epitaxial structure connecting the first semiconductor nanostructure and a second epitaxial structure connecting the second semiconductor nanostructure. The semiconductor device structure further includes a gate stack wrapped around the first semiconductor nanostructure and the second semiconductor nanostructure. In addition, the semiconductor device structure includes a conductive contact electrically connected to the epitaxial structures. The conductive contact has a portion extending towards the gate stack from terminals of the first epitaxial structure and the second epitaxial structures. The first epitaxial structure is wider than the portion of the conductive contact.

公开(公告)号：US11637062B2

公开(公告)日：2023-04-25

申请号：US17676719

申请日：2022-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Khaderbad Mrunal Abhijith ,  Yu-Yun Peng ,  Fu-Ting Yen ,  Chen-Han Wang ,  Tsu-Hsiu Perng ,  Keng-Chu Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.

公开(公告)号：US11011413B2

公开(公告)日：2021-05-18

申请号：US16354362

申请日：2019-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Shuen-Shin Liang ,  Jung-Hao Chang ,  Chia-Hung Chu ,  Keng-Chu Lin

IPC: H01L21/768

Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

公开(公告)号：US10761427B2

公开(公告)日：2020-09-01

申请号：US15156019

申请日：2016-05-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Keng-Chu Lin ,  Joung-Wei Liou ,  Cheng-Han Wu ,  Ya Hui Chang

IPC: G03F7/038 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  G03F7/039 ,  G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32

Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

公开(公告)号：US10134632B2

公开(公告)日：2018-11-20

申请号：US15425558

申请日：2017-02-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joung-Wei Liou ,  Hui-Chun Yang ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/31 ,  H01L23/48

Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.