公开(公告)号：US09425239B2

公开(公告)日：2016-08-23

申请号：US14737372

申请日：2015-06-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Julien Delalleau

IPC: H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L23/528 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L27/115 ,  H01L29/78

CPC classification number: H01L43/12 ,  H01L21/26513 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11507 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/42356 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.

Abstract translation: 本公开涉及一种半导体衬底上的存储器，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，该选择晶体管具有连接到选择线的控制栅极， 连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成于所述衬底中的沟槽中产生的嵌入垂直栅极和与所述衬底相对的沟道区域 沟槽的第一面，位于耦合到可变阻抗元件的衬底的表面上的第一深掺杂区域和第二掺杂区域之间。

公开(公告)号：US20140191179A1

公开(公告)日：2014-07-10

申请号：US14150596

申请日：2014-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

Abstract translation: 本公开涉及包括晶体管的集成电路，该晶体管包括第一和第二导电端子以及控制端子。 集成电路还包括第一介电层，导电层和第二介电层的堆叠，第一导电端子包括形成在第一介电层中的第一半导体区域，该控制端子包括形成在第一介电层中的第二半导体区域 导电层，第二导电端子包括形成在第二介电层中的第三半导体区域。

公开(公告)号：US12057513B2

公开(公告)日：2024-08-06

申请号：US18210155

申请日：2023-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Brice Arrazat ,  Julien Delalleau ,  Joel Metz

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/94 ,  H01L49/02 ,  H10B41/35

CPC classification number: H01L29/945 ,  H01L21/2652 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/788 ,  H10B41/35

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US11721773B2

公开(公告)日：2023-08-08

申请号：US17366585

申请日：2021-07-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Brice Arrazat ,  Julien Delalleau ,  Joel Metz

IPC: H01L21/00 ,  H01L29/94 ,  H01L21/28 ,  H01L21/265 ,  H01L49/02 ,  H01L29/423 ,  H01L29/788 ,  H10B41/35

CPC classification number: H01L29/945 ,  H01L21/2652 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/788 ,  H10B41/35

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US20210225853A1

公开(公告)日：2021-07-22

申请号：US17220286

申请日：2021-04-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H01L27/1157 ,  G11C5/06 ,  H01L27/11565

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US10763213B2

公开(公告)日：2020-09-01

申请号：US16037595

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L23/535 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28 ,  H01L23/528 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11 ,  H01L29/49

Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.

公开(公告)号：US10686046B2

公开(公告)日：2020-06-16

申请号：US16513145

申请日：2019-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/04 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  H01L21/306

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US10366757B2

公开(公告)日：2019-07-30

申请号：US16126316

申请日：2018-09-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  G11C16/12 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  G11C16/10

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

公开(公告)号：US10128314B2

公开(公告)日：2018-11-13

申请号：US15398228

申请日：2017-01-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L21/8224 ,  H01L21/336 ,  H01L21/337 ,  H01L27/24 ,  H01L29/732 ,  H01L29/66 ,  H01L45/00

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

公开(公告)号：US20170117326A1

公开(公告)日：2017-04-27

申请号：US15398228

申请日：2017-01-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L29/732

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.