公开(公告)号：US20240379653A1

公开(公告)日：2024-11-14

申请号：US18782939

申请日：2024-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Traynor ,  Tanya Abaya ,  Dharmendar Palle ,  Mark S. Rodder

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/528

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

公开(公告)号：US12046635B2

公开(公告)日：2024-07-23

申请号：US17510753

申请日：2021-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho Do ,  Rwik Sengupta

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0696 ,  H01L29/0847 ,  H01L29/7827

Abstract: A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.

公开(公告)号：US10566330B2

公开(公告)日：2020-02-18

申请号：US15977949

申请日：2018-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Palle ,  Rwik Sengupta ,  Mohammad Ali Pourghaderi

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.

公开(公告)号：US10381315B2

公开(公告)日：2019-08-13

申请号：US15927239

申请日：2018-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L31/062 ,  H01L23/00 ,  H01L23/522 ,  H01L27/02 ,  H04L9/32 ,  H01L23/532

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

公开(公告)号：US20190148502A1

公开(公告)日：2019-05-16

申请号：US16121427

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02

Abstract: A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US20190148298A1

公开(公告)日：2019-05-16

申请号：US15948543

申请日：2018-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L23/535 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US10164121B2

公开(公告)日：2018-12-25

申请号：US15181327

申请日：2016-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic ,  Joon Goo Hong ,  Rwik Sengupta

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.

公开(公告)号：US09728502B2

公开(公告)日：2017-08-08

申请号：US14920867

申请日：2015-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh Hegde ,  Mark Rodder ,  Rwik Sengupta ,  Chris Bowen

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L2221/1089

Abstract: A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier.

公开(公告)号：US09691860B2

公开(公告)日：2017-06-27

申请号：US14698817

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Rwik Sengupta

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795

Abstract: A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.

公开(公告)号：US20170148922A1

公开(公告)日：2017-05-25

申请号：US15181327

申请日：2016-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic ,  Joon Goo Hong ,  Rwik Sengupta

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78645

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.