公开(公告)号：US20220187942A1

公开(公告)日：2022-06-16

申请号：US17432275

申请日：2020-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghun KWAK ,  Daehyun YOO ,  Bongjun KO ,  Mansung KIM ,  Jaeho LEE ,  Junghoon CHOI ,  Changjin KIM ,  Sangheon PARK ,  Jongdae PARK

IPC: G06F3/041 ,  G06F3/044

Abstract: According to an embodiment, an electronic device may include: a processor; and a touch circuit configured to output, to the processor, information associated with a touch on at least one surface of the electronic device. The touch circuit may be configured to: generate first raw data including a first value associated with capacitance for each of multiple channels of the touch circuit; generate a first baseline on the basis of the first raw data; identify whether the first raw data satisfies a designated condition; and identify whether the first baseline is reset, on the basis of whether the raw data satisfies the designated condition.

公开(公告)号：US20200266153A1

公开(公告)日：2020-08-20

申请号：US16866033

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20190157212A1

公开(公告)日：2019-05-23

申请号：US16257189

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53209 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5226

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20180358470A1

公开(公告)日：2018-12-13

申请号：US15892850

申请日：2018-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho LEE ,  Haeryong KIM ,  Sanghyun JO ,  Hyeonjin SHIN

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L27/11521 ,  G11C11/54 ,  G11C11/56

CPC classification number: H01L29/7887 ,  B82Y10/00 ,  G11C11/54 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C13/025 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5612 ,  G11C2213/35 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/0673 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/49 ,  H01L29/78684 ,  H01L29/78687

Abstract: Provided are nonvolatile memory devices including 2-dimensional (2D) material and apparatuses including the nonvolatile memory devices. A nonvolatile memory device may include a storage stack including a plurality of charge storage layers between a channel element and a gate electrode facing the channel element. The plurality of charge storage layers may include a 2D material. An interlayer barrier layer may be further provided between the plurality of charge storage layers. The nonvolatile memory device may have a multi-bit or multi-level memory characteristic due to the plurality of charge storage layers.

公开(公告)号：US20180190800A1

公开(公告)日：2018-07-05

申请号：US15904967

申请日：2018-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungeun BYUN ,  Jisoo KYOUNG ,  Seongjun PARK ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Jaeho LEE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/66977 ,  H01L29/456 ,  H01L29/78

Abstract: An electronic device includes a semiconductor layer, a tunneling layer formed of a material including a two-dimensional (2D) material so as to directly contact a certain region of the semiconductor layer, and a metal layer formed on the tunneling layer.

公开(公告)号：US20160322486A1

公开(公告)日：2016-11-03

申请号：US14932392

申请日：2015-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho LEE ,  Kiyoung Lee ,  Sangyeob Lee ,  Eunkyu Lee ,  Jinseong Heo ,  Seongjun Park

IPC: H01L29/778 ,  H01L23/00 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/778 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/66477 ,  H01L29/78603 ,  H01L29/78684

Abstract: A method of manufacturing a flexible device including a two-dimensional (2D) material, e.g., graphene, includes forming a dielectric layer on a first substrate, forming a two-dimensional (2D) material layer on the dielectric layer; forming a pattern in the 2D material layer, forming a second substrate on the dielectric layer and the 2D material layer, the first substrate including a flexible material, removing the first substrate, and forming a source electrode, a drain electrode, and a gate electrode on the dielectric layer.

Abstract translation: 一种制造包括诸如石墨烯的二维（2D）材料的柔性器件的方法包括在第一衬底上形成电介质层，在电介质层上形成二维（2D）材料层; 在所述2D材料层中形成图案，在所述介电层和所述2D材料层上形成第二基板，所述第一基板包括柔性材料，去除所述第一基板，以及形成源电极，漏电极和栅电极 在介电层上。

公开(公告)号：US20230320078A1

公开(公告)日：2023-10-05

申请号：US18331493

申请日：2023-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho LEE ,  Boeun PARK ,  Yongsung KIM ,  Jooho LEE

IPC: H10B12/00 ,  G11C11/22 ,  H01L29/51 ,  G01G7/00 ,  G01G7/06 ,  G11C19/00 ,  G11C19/18

CPC classification number: H10B12/37 ,  H01L28/56 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2275 ,  H01L29/516 ,  G01G7/00 ,  G01G7/06 ,  G11C19/005 ,  G11C19/18 ,  H10B12/33

Abstract: A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation:





V
MAX

=


(

1
+



❘
"\[LeftBracketingBar]"


Z
2


❘
"\[RightBracketingBar]"




❘
"\[LeftBracketingBar]"


Z
1


❘
"\[RightBracketingBar]"




)

⁢

t
F

⁢

E
FM






where VMAX is a capacitance boosting operating voltage, Z1 is impedance of the ferroelectric film, Z2 is impedance of the dielectric film, tF is a thickness of the ferroelectric film, and EFM is an electric field applied to the ferroelectric film having a maximum polarization.

公开(公告)号：US20210358694A1

公开(公告)日：2021-11-18

申请号：US17116097

申请日：2020-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho LEE ,  Boeun PARK ,  Yongsung KIM ,  Jooho LEE

IPC: H01G7/06 ,  H01L49/02

Abstract: A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation: V MAX = ( 1 +  Z 2   Z 1  ) ⁢ t F ⁢ E FM where VMAX is a capacitance boosting operating voltage, Z1 is impedance of the ferroelectric film, Z2 is impedance of the dielectric film, tF is a thickness of the ferroelectric film, and EFM is an electric field applied to the ferroelectric film having a maximum polarization.

公开(公告)号：US20210327817A1

公开(公告)日：2021-10-21

申请号：US17362308

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20210265458A1

公开(公告)日：2021-08-26

申请号：US17060911

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggyu SONG ,  Younsoo KIM ,  Jaeho LEE

IPC: H01L49/02 ,  H01L27/108

Abstract: A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al2O3 film between the top electrode and the dielectric film, wherein the doped Al2O3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al2O3.