公开(公告)号：US11335683B2

公开(公告)日：2022-05-17

申请号：US16917451

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  ChihWei Kuo ,  Junjing Bao

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: A transistor channel profile structure may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include different fin profiles for the NMOS transistors and the PMOS transistors, such as the NMOS fins are thicker than the PMOS fins or the NMOS fin has a straight vertical surface and the PMOS fin has a notch at a fin bottom region. In still another example, a transistor circuit may include different nano-sheet profiles for a NMOS GAA device and a PMOS GAA device where the NMOS nano-sheet is thicker than the PMOS nano-sheet. Such configurations optimize the NMOS and the PMOS transistors with the NMOS having a low channel resistance while the PMOS has a lower short channel effect.

公开(公告)号：US11164952B2

公开(公告)日：2021-11-02

申请号：US16812292

申请日：2020-03-07

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Haining Yang ,  Junjing Bao

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A gate all around transistor may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include a dielectric or air gap as an insulator between the channels of the transistors in the circuit. In another example, a transistor may include a first channel surrounded by a first metal, a second channel surrounded by a second metal proximate to the first channel, and an insulator, such as a dielectric or air gap, between the first metal and the second metal. The insulator helps reduce the parasitic capacitance between the source/drain regions and the metal fill regions of the transistor.

公开(公告)号：US11139315B2

公开(公告)日：2021-10-05

申请号：US16669837

申请日：2019-10-31

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H01L27/11 ,  H01L29/51 ,  H01L29/78 ,  H01L27/1159 ,  H01L29/66 ,  H01L21/28

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a ferroelectric (FE) semiconductor device having a channel region; a gate oxide; a FE region, wherein the gate oxide is disposed between the FE region and the channel region; a gate region, wherein the FE region is disposed between the gate oxide and the gate region; a first semiconductor region disposed adjacent to the channel region; and a second semiconductor region disposed adjacent to the channel region. The semiconductor device may also include a transistor, wherein a region of the transistor is connected to the gate region, the first semiconductor region, or the second semiconductor region of the FE semiconductor device.

公开(公告)号：US11121132B2

公开(公告)日：2021-09-14

申请号：US16678320

申请日：2019-11-08

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang

IPC: H01L21/76 ,  H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a gate-cut isolation structure. An example method of fabricating semiconductor device generally includes forming a dielectric region between a first semiconductor region and a second semiconductor region. The method also includes forming a first gate region disposed above and spanning a width of the dielectric region between the first and second semiconductor regions, wherein the first gate region is also disposed above at least a portion of the first semiconductor region and above at least a portion of the second semiconductor region. The method further includes concurrently forming an SDB and a gate-cut isolation structure, wherein the SDB intersects the first and second semiconductor regions and wherein the gate-cut isolation structure electrically separates the first gate region into a first portion associated with the first semiconductor region and a second portion associated with the second semiconductor region.

公开(公告)号：US11038344B2

公开(公告)日：2021-06-15

申请号：US16362417

申请日：2019-03-22

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Xiangdong Chen ,  Haining Yang ,  Kern Rim

IPC: H02H9/04 ,  H02J7/00 ,  H01Q1/22

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

公开(公告)号：US10854604B1

公开(公告)日：2020-12-01

申请号：US16578101

申请日：2019-09-20

Applicant: QUALCOMM Incorporated

Inventor： ChihWei Kuo ,  Haining Yang ,  Jun Yuan ,  Kern Rim

IPC: H01L27/092 ,  H03K19/0185 ,  H02M7/515

Abstract: Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.

公开(公告)号：US10825536B1

公开(公告)日：2020-11-03

申请号：US16556505

申请日：2019-08-30

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Periannan Chidambaram

IPC: G11C17/14 ,  G11C17/16 ,  G11C17/18 ,  G06N3/08 ,  G06N20/00 ,  G11C13/00

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for programming a device having one or more programmable circuits to implement, for example, a machine learning model. One example apparatus generally includes a plurality of word lines, a plurality of bit lines, and an array of programmable circuits. Each programmable circuit is coupled to a corresponding word line in the plurality of word lines and to a corresponding bit line in the plurality of bit lines and comprises: a main resistor coupled between the corresponding word line and the corresponding bit line, an auxiliary resistor, a fuse coupled in series with the auxiliary resistor, wherein the auxiliary resistor and the fuse are coupled between the corresponding word line and the corresponding bit line, and a programming circuit configured to selectively blow the fuse.

公开(公告)号：US20200168607A1

公开(公告)日：2020-05-28

申请号：US16203205

申请日：2018-11-28

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238

Abstract: Circuits employing asymmetric diffusion breaks in different type semiconductor diffusion regions are disclosed. In examples herein, diffusion breaks having dimensions asymmetric to each other are provided in different types of diffusion regions in a circuit to increase carrier mobility in semiconductor channels of a semiconductor device formed in different diffusion regions. In examples herein, the circuit includes a P-type and N-type semiconductor device(s) formed in a P-type and an N-type diffusion region(s), respectively, formed in the substrate. Complementary metal oxide semiconductor (CMOS) circuits can be realized from the P-type and N-type semiconductor devices. Diffusion breaks can induce strain in the diffusion regions with a magnitude of the induced strain related to a dimension of the diffusion breaks. As one example, an induced tensile strain may increase carrier mobility in N-type devices and decrease carrier mobility in P-type devices, with induced compressive strain having the opposite effect.

公开(公告)号：US10483200B1

公开(公告)日：2019-11-19

申请号：US16143647

申请日：2018-09-27

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen ,  John Jianhong Zhu

IPC: H01L21/00 ,  H01L23/522 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

Abstract: Integrated circuits (ICs) employing additional output vertical interconnect access(es) (via(s)) coupled to a circuit output via to decrease circuit output resistance and related methods are disclosed. In exemplary aspects, an output metal interconnect is formed in the IC that extends between a first output contact connected to an output transistor(s) of a circuit, and across an adjacent dummy gate to a second output contact area on the opposite side of the dummy gate from the signal output node. A second output via is connected to the output metal interconnect in the second output contact area. A metal line in a metal layer above the diffusion area and metal contacts is connected to the output via and second output via having parallel output via resistances to reduce the output via resistance of the output transistor(s) of the circuit, and thus reduces the overall resistance of the signal output node of the circuit.

公开(公告)号：US10062763B2

公开(公告)日：2018-08-28

申请号：US14723199

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Haining Yang ,  Yanxiang Liu ,  Jeffrey Junhao Xu

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.