公开(公告)号：US20130134533A1

公开(公告)日：2013-05-30

申请号：US13683783

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Xiaochun Zhu ,  Matthew Nowak ,  Xia Li ,  Seung H. Kang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract translation: 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

公开(公告)号：US11790241B2

公开(公告)日：2023-10-17

申请号：US17016130

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Matthias Reisser ,  Saurabh Kedar Pitre ,  Xiaochun Zhu ,  Edward Harrison Teague ,  Zhongze Wang ,  Max Welling

IPC: G06F17/16 ,  G06N3/10 ,  G06N3/047

CPC classification number: G06N3/10 ,  G06F17/16 ,  G06N3/047

Abstract: In one embodiment, a method of simulating an operation of an artificial neural network on a binary neural network processor includes receiving a binary input vector for a layer including a probabilistic binary weight matrix and performing vector-matrix multiplication of the input vector with the probabilistic binary weight matrix, wherein the multiplication results are modified by simulated binary-neural-processing hardware noise, to generate a binary output vector, where the simulation is performed in the forward pass of a training algorithm for a neural network model for the binary-neural-processing hardware.

公开(公告)号：US10777259B1

公开(公告)日：2020-09-15

申请号：US16415204

申请日：2019-05-17

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C11/412 ,  G06N3/02 ,  H03K19/21 ,  G11C11/418

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for convolution computation. One example apparatus generally includes a static random-access memory (SRAM) having a plurality of memory cells. Each of the plurality of memory cells may include a flip-flop (FF) having an output node and a complementary output node; a first switch coupled between the output node and a bit line (BL) of the SRAM, the first switch having a control input coupled to a word line (WL) of the SRAM; and a second switch coupled between the complementary output node and a complementary bit line (BLB) of the SRAM, the second switch having another control input coupled to a complementary word line (WLB) of the SRAM.

公开(公告)号：US10043967B2

公开(公告)日：2018-08-07

申请号：US14454509

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Xiaochun Zhu ,  Xia Li ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

公开(公告)号：US09496314B1

公开(公告)日：2016-11-15

申请号：US14853116

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L29/66 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L21/8234

CPC classification number: H01L27/228 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L21/823475 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Shared source line magnetic tunnel junction (MTJ) bit cells employing uniform MTJ connection patterns for reduced area are disclosed. In one aspect, a two (2) transistor, two (2) MTJ (2T2MTJ) bit cell includes a shared source line system having first and second source lines. A uniform MTJ connection pattern results in the first source line disposed in an upper metal layer and electrically coupled to a free layer of a first MTJ, and the second source line disposed in a lower metal layer and electrically coupled to a second access transistor. Middle segments are disposed in middle metal layers to reserve the middle metal layers for strap segments of a strap cell that may be used to electrically couple the first and second source lines. Electrically coupling the first and second source lines using the strap cell allows each MTJ to logically share a single source line.

Abstract translation: 公开了采用均匀MTJ连接图案的共享源极线磁隧道结（MTJ）位单元，以减小面积。 一方面，两（2）晶体管，两（2）MTJ（2T2MTJ）位单元包括具有第一和第二源极线的共享源极线系统。 均匀的MTJ连接图案使得第一源极线设置在上金属层中并电耦合到第一MTJ的自由层，并且第二源极线设置在下金属层中并电耦合到第二存取晶体管。 中间部分设置在中间金属层中，以保留可用于电耦合第一和第二源极线的带状电池的带段的中间金属层。 使用带单元电连接第一和第二源极线允许每个MTJ在逻辑上共享单个源极线。

公开(公告)号：US09489999B2

公开(公告)日：2016-11-08

申请号：US14555434

申请日：2014-11-26

Applicant: QUALCOMM Incorporated

Inventor： Brian Marc Rosenberg ,  Xiaochun Zhu ,  Xu Guo

IPC: G11C11/00 ,  G11C11/16 ,  G09C1/00 ,  H04L9/08 ,  H04L9/32 ,  G11C16/20

CPC classification number: G11C11/1673 ,  G09C1/00 ,  G11C11/1675 ,  G11C11/1695 ,  G11C16/20 ,  H04L9/0866 ,  H04L9/3278

Abstract: A method includes coupling a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit. The method also includes comparing, at the comparison circuit, a first resistance of the first MTJ element to a second resistance of the second MTJ element. The method further includes generating a first physical unclonable function (PUF) output bit based on a result of comparing the first resistance to the second resistance.

Abstract translation: 一种方法包括将第一磁隧道结（MTJ）元件和第二MTJ元件耦合到比较电路。 该方法还包括在比较电路中比较第一MTJ元件的第一电阻与第二MTJ元件的第二电阻。 该方法还包括基于将第一电阻与第二电阻进行比较的结果来产生第一物理不可克隆功能（PUF）输出位。

公开(公告)号：US20160254318A1

公开(公告)日：2016-09-01

申请号：US14856316

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic random access memory (MRAM) bit cells employing source lines and/or bit lines disposed in multiple, stacked metal layers to reduce MRAM bit cell resistance are disclosed. Related methods and systems are also disclosed. In aspects disclosed herein, MRAM bit cells are provided in a memory array. The MRAM bit cells are fabricated in an integrated circuit (IC) with source lines and/or bit lines formed by multiple, stacked metal layers disposed above a semiconductor layer to reduce the resistance of the source lines. In this manner, if node size in the IC is scaled down, the resistance of the source lines and/or the bit lines can be maintained or reduced to avoid an increase in drive voltage that generates a write current for write operations for the MRAM bit cells.

Abstract translation: 公开了使用设置在多个堆叠金属层中的源极线和/或位线的磁性随机存取存储器（MRAM）位单元，以减少MRAM位单元电阻。 还公开了相关方法和系统。 在本文公开的方面，MRAM位单元被提供在存储器阵列中。 在集成电路（IC）中制造MRAM位单元，源极线和/或位线由设置在半导体层上方的多个堆叠金属层形成，以减小源极线的电阻。 以这种方式，如果IC中的节点尺寸按比例缩小，则可以维持或减小源极线和/或位线的电阻，以避免产生用于MRAM位的写入操作的写入电流的驱动电压的增加 细胞。

公开(公告)号：US20160148666A1

公开(公告)日：2016-05-26

申请号：US14555434

申请日：2014-11-26

Applicant: QUALCOMM Incorporated

Inventor： Brian Marc Rosenberg ,  Xiaochun Zhu ,  Xu Guo

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G09C1/00 ,  G11C11/1675 ,  G11C11/1695 ,  G11C16/20 ,  H04L9/0866 ,  H04L9/3278

Abstract: A method includes coupling a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit. The method also includes comparing, at the comparison circuit, a first resistance of the first MTJ element to a second resistance of the second MTJ element. The method further includes generating a first physical unclonable function (PUF) output bit based on a result of comparing the first resistance to the second resistance.

Abstract translation: 一种方法包括将第一磁隧道结（MTJ）元件和第二MTJ元件耦合到比较电路。 该方法还包括在比较电路中比较第一MTJ元件的第一电阻与第二MTJ元件的第二电阻。 该方法还包括基于将第一电阻与第二电阻进行比较的结果来产生第一物理不可克隆功能（PUF）输出位。

公开(公告)号：US09343135B2

公开(公告)日：2016-05-17

申请号：US14072537

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  G09C1/00 ,  H04L9/08 ,  H04L9/32

CPC classification number: G11C11/1695 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage.

Abstract translation: 一个特征涉及实现物理上不可克隆功能的方法。 该方法包括将磁阻随机存取存储器（MRAM）单元的阵列初始化为第一逻辑状态，其中每个MRAM单元具有大于第一电压且小于第二电压的随机转变电压。 转换电压表示使MRAM单元从第一逻辑状态转换到第二逻辑状态的电压电平。 该方法还包括将编程信号电压施加到阵列的每个MRAM单元，以使阵列的MRAM单元的至少一部分随机地将状态从第一逻辑状态改变到第二逻辑状态，其中编程信号 电压大于第一电压且小于第二电压。

公开(公告)号：US09324404B2

公开(公告)日：2016-04-26

申请号：US14156541

申请日：2014-01-16

Applicant: QUALCOMM Incorporated

Inventor： Hari M. Rao ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/12 ,  G11C7/14 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/004 ,  H01L43/12 ,  Y10T29/49117

Abstract: Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation.

Abstract translation: 使用磁退火参考单元读取/感测存储在磁阻随机存取存储器（MRAM）单元中的数据的系统和方法。 MRAM包括包括至少一个磁存储单元的参考电路，其中MRAM中的每个磁存储单元被编程为相同的状态。 参考电路包括耦合到磁存储单元的负载元件，其中负载元件被配置为在读取操作期间建立参考电压。