公开(公告)号：US09875784B1

公开(公告)日：2018-01-23

申请号：US15486891

申请日：2017-04-13

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: G11C11/22 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/11597

CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275 ,  H01L21/28291 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/516 ,  H01L29/78391

Abstract: A three-dimensional (3D) ferroelectric dipole metal-oxide semiconductor ferroelectric field-effect transistor (MOSFeFET) system, and related methods and systems are disclosed. The 3D ferroelectric dipole MOSFeFET system includes a bottom dielectric layer, a gate layer disposed above the bottom dielectric layer, and a top dielectric layer disposed on top of the gate layer. The 3D ferroelectric dipole MOSFeFET system also includes at least one source line (SL) line and at least one bit line (BL). At least one interconnect, which extends between the bottom dielectric layer and the top dielectric layer interconnects the at least one SL with the at least one BL. A ferroelectric dipole MOSFeFET(s) is formed at an intersection area of the at least one interconnect and the gate layer. The 3D ferroelectric dipole MOSFeFET system can lead to improved component density and reduced footprint.

公开(公告)号：US09865798B2

公开(公告)日：2018-01-09

申请号：US14630438

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Junjing Bao ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L21/768 ,  H01L21/31 ,  H01L21/311 ,  H01L21/321 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L23/544 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor device includes an interconnect layer and a bottom electrode of a resistive memory device. The bottom electrode is coupled to the interconnect layer, and the bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

公开(公告)号：US09842638B1

公开(公告)日：2017-12-12

申请号：US15414855

申请日：2017-01-25

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: G11C29/00 ,  G11C11/16

CPC classification number: G11C11/1697 ,  G11C11/1675 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5002

Abstract: Dynamically controlling voltage for access (i.e., read and/or write) operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations in MTJs that affect MTJ resistance, which can change write current at a given fixed supply voltage applied to an MRAM bit cell. The MRAM bit cell PVMC may also be configured to measure process variations in logic circuits representing process variations in access transistors employed in MRAM bit cells. These measured process variations in MTJs and/or logic circuits are used to dynamically determine a supply voltage for access operations to MRAM.

公开(公告)号：US09824735B1

公开(公告)日：2017-11-21

申请号：US15237078

申请日：2016-08-15

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Jianan Kan ,  Chando Park ,  Peiyuan Wang ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C11/16 ,  G06F7/58

CPC classification number: G11C11/161 ,  G06F7/588 ,  G11C7/24 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1695 ,  G11C11/1697 ,  G11C11/18

Abstract: An apparatus includes a perpendicular magnetic tunnel junction (MTJ) including a free layer. The apparatus includes a spin orbit torque metal layer coupled to the perpendicular MTJ and configured to change a magnetization state of the free layer responsive to flow of a current along the spin orbit torque metal layer. The apparatus includes a random number generator configured to generate a random number at least partially based on a state of the perpendicular MTJ.

公开(公告)号：US09800271B2

公开(公告)日：2017-10-24

申请号：US14852988

申请日：2015-09-14

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Sara Choi ,  Byung Kyu Song ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim ,  Seung Hyuk Kang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

公开(公告)号：US09754654B1

公开(公告)日：2017-09-05

申请号：US15414855

申请日：2017-01-25

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: G11C29/00 ,  G11C11/16

Abstract: Dynamically controlling voltage for access (i.e., read and/or write) operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations in MTJs that affect MTJ resistance, which can change write current at a given fixed supply voltage applied to an MRAM bit cell. The MRAM bit cell PVMC may also be configured to measure process variations in logic circuits representing process variations in access transistors employed in MRAM bit cells. These measured process variations in MTJs and/or logic circuits are used to dynamically determine a supply voltage for access operations to MRAM.

公开(公告)号：US09753874B2

公开(公告)日：2017-09-05

申请号：US14627318

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

IPC: G06F13/28 ,  G06F12/02 ,  G06F9/44

CPC classification number: G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

公开(公告)号：US09666792B2

公开(公告)日：2017-05-30

申请号：US14824507

申请日：2015-08-12

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L21/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of MTJ elements can provide reduced free layer sizing for enhanced MTJ operational margin. In certain aspects, to reduce size of a free layer during fabrication of an MTJ to provide enhanced write and retention symmetry, ion beam etching (IBE) fabrication process is employed to fabricate a free layer smaller than the pinned layer. To avoid asymmetrical footing being fabricated in free layer due to shadow-effect of neighboring MTJs, an ion beam directed at the MTJ is shadow-effect compensated. The angle of incidence of the ion beam directed at the MTJ is varied as the MTJ is rotated to be less steep when another MTJ is in directional line of the ion beam and the MTJ being fabricated. Thus, the free layer is etched more uniformly in the MTJ while avoiding increased etching damage.

公开(公告)号：US09614147B2

公开(公告)日：2017-04-04

申请号：US15169603

申请日：2016-05-31

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L43/10 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes a free layer. The MTJ also includes a barrier layer coupled to the free layer. The MTJ also has a fixed layer, coupled to the barrier layer. The fixed layer includes a first synthetic antiferromagnetic (SAF) multilayer having a first perpendicular magnetic anisotropy (PMA) and a first damping constant. The fixed layer also includes a second SAF multilayer having a second perpendicular magnetic anisotropy (PMA) and a second damping constant lower than the first damping constant. The first SAF multilayer is closer to the barrier layer than the second SAF multilayer. The fixed layer also includes a SAF coupling layer between the first and the second SAF multilayers.

公开(公告)号：US20170077387A1

公开(公告)日：2017-03-16

申请号：US14856372

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Jianan Kan ,  Matthias Georg Gottwald ,  Xiaochun Zhu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01F10/3263 ,  H01F10/3286 ,  H01F41/307 ,  H01L43/08

Abstract: Magnetic Tunnel Junction (MTJ) devices particularly suited for efficient spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM) are disclosed. In one aspect, a MTJ structure with a reduced thickness first pinned layer provided below a tunnel magneto-resistance (TMR) barrier layer is provided. The first pinned layer provided below the TMR bather layer includes one pinned layer magnetized in only one magnetic orientation. In another aspect, a second pinned layer and a spacer layer are provided above a free layer and the TMR barrier layer in the MTJ. The second pinned layer is magnetized in a magnetic orientation that is anti-parallel to that of the first pinned layer. In yet another aspect, a giant magneto-resistance (GMR) spacer layer is provided as the spacer layer between the second pinned layer and the free layer in the MTJ.

Abstract translation: 公开了特别适用于高效自旋转矩传递（STT）磁随机存取存储器（MRAM）（STT MRAM）的磁隧道结（MTJ）装置。 在一个方面，提供了一种在隧道磁阻（TMR）阻挡层下方提供具有减小厚度的第一固定层的MTJ结构。 在TMR沐浴层下面提供的第一被钉扎层包括仅以一个磁性取向磁化的一个钉扎层。 在另一方面，第二被钉扎层和间隔层设置在自由层上方和MTJ中的TMR阻挡层之上。 第二被钉扎层被磁化成与第一被钉扎层反平行的磁取向。 在另一方面，提供巨磁电阻（GMR）间隔层作为MTJ中的第二被钉扎层和自由层之间的间隔层。