-
公开(公告)号：US11869826B2
公开(公告)日：2024-01-09
申请号：US17030144
申请日：2020-09-23
IPC分类号： H01L23/467 , H01L25/10 , H01L25/00
CPC分类号： H01L23/467 , H01L25/105 , H01L25/50 , H01L2225/1094
摘要： An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.
-
32.发明申请公开(公告)号：US20230087329A1
公开(公告)日：2023-03-23
申请号：US18053201
申请日：2022-11-07
IPC分类号： G11C16/14 , G11C16/30 , G11C17/16 , G11C17/18 , G11C16/22 , G11C13/00 , G11C11/16 , G11C11/22 , G11C16/08
摘要： Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.
-
公开(公告)号：US20230069576A1
公开(公告)日：2023-03-02
申请号：US17463318
申请日：2021-08-31
摘要： A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.
-
公开(公告)号：US11586958B2
公开(公告)日：2023-02-21
申请号：US16840916
申请日：2020-04-06
发明人： Di Wu , Anthony D. Veches , James S. Rehmeyer , Debra M. Bell , Libo Wang
摘要： Embodiments of the disclosure are drawn to apparatuses, systems, methods for performing operations associated with machine learning. Machine learning operations may include processing a data set, training a machine learning algorithm, and applying a trained algorithm to a data set. Some of the machine learning operations, such as pattern matching operations, may be performed within a memory device.
-
35.发明申请公开(公告)号：US20230021201A1
公开(公告)日：2023-01-19
申请号：US17939908
申请日：2022-09-07
IPC分类号： G11C11/406 , G11C11/4076 , G11C11/4074 , G11C5/14
摘要： Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.
-
公开(公告)号：US20220366998A1
公开(公告)日：2022-11-17
申请号：US17876769
申请日：2022-07-29
IPC分类号： G11C29/44 , G11C11/408
摘要： A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.
-
37.发明授权公开(公告)号：US11495299B2
公开(公告)日：2022-11-08
申请号：US17339846
申请日：2021-06-04
IPC分类号： G11C16/14 , G11C16/30 , G11C17/16 , G11C17/18 , G11C16/22 , G11C13/00 , G11C11/16 , G11C11/22 , G11C16/08
摘要： Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.
-
公开(公告)号：US11410715B2
公开(公告)日：2022-08-09
申请号：US17091969
申请日：2020-11-06
IPC分类号： G11C11/405 , G11C11/406 , G06F3/06 , H01L25/065
摘要： Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.
-
公开(公告)号：US11309012B2
公开(公告)日：2022-04-19
申请号：US17187002
申请日：2021-02-26
IPC分类号： G11C11/406 , G11C11/408
摘要： Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. A memory device may include a number of memory banks, at least some of which may be simultaneously entered into a refresh mode. A given memory bank may perform an auto-refresh operation or a targeted refresh operation, which may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered between the refreshing memory banks, such that a portion of the refreshing memory banks are performing a targeted refresh operation simultaneously with a portion of the refreshing memory banks performing an auto-refresh operation.
-
公开(公告)号：US11276454B2
公开(公告)日：2022-03-15
申请号：US16939669
申请日：2020-07-27
发明人： Dale H. Hiscock , Debra M. Bell , Michael Kaminski , Joshua E. Alzheimer , Anthony D. Veches , James S. Rehmeyer
IPC分类号： G11C16/34 , G11C11/406 , G11C11/4074 , G11C16/10 , G11C11/4072
摘要： Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.
-
-
-
-
-
-
-
-
-
搜索结果
151 条记录 (耗时 0.029 秒)
