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公开(公告)号：US12079076B2
公开(公告)日：2024-09-03
申请号：US17591362
申请日：2022-02-02
发明人： Yoshinori Fujiwara , Vivek Kotti , Christopher G. Wieduwilt , Jason M. Johnson , Kevin G. Werhane
IPC分类号： G06F11/00 , G06F11/10 , G11C11/408 , G11C11/4096
CPC分类号： G06F11/1068 , G06F11/1032 , G06F11/1044 , G11C11/4085 , G11C11/4087 , G11C11/4096
摘要： Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
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公开(公告)号：US20240071560A1
公开(公告)日：2024-02-29
申请号：US17822032
申请日：2022-08-24
CPC分类号： G11C29/789 , G11C29/4401 , G11C29/46
摘要： An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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公开(公告)号：US11791011B1
公开(公告)日：2023-10-17
申请号：US17735528
申请日：2022-05-03
发明人： Takuya Tamano , Yoshinori Fujiwara
CPC分类号： G11C29/4401 , G11C29/12
摘要： Methods, systems, and devices for self-repair verification are described. A memory system may receive, at a memory device, a command to initiate a repair operation. The memory system may perform the repair operation by replacing a first row of memory cells of the memory device with a second row of memory cells of the memory device. The memory system may write first data to the second row of memory cells, and read second data from the second row of memory cells, based on a stored indication associated with the replacement of rows. The memory device may output an error flag with a first value based at least in part on reading the second data, and the first value of the error flag may indicate that the repair operation was successfully performed based at least in part on the second data matching the first data.
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公开(公告)号：US20230020753A1
公开(公告)日：2023-01-19
申请号：US17305878
申请日：2021-07-16
发明人： Yoshinori Fujiwara , Harish V. Gadamsetty , Gary Howe , Dennis G. Montierth , Michael A. Shore , Jason M. Johnson
IPC分类号： G11C11/406 , G11C11/408 , G11C29/00 , G11C29/44
摘要： Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).
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公开(公告)号：US20220366998A1
公开(公告)日：2022-11-17
申请号：US17876769
申请日：2022-07-29
IPC分类号： G11C29/44 , G11C11/408
摘要： A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.
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公开(公告)号：US11170837B1
公开(公告)日：2021-11-09
申请号：US16860498
申请日：2020-04-28
IPC分类号： G11C11/22 , G11C11/4096 , G11C29/04 , G11C11/4094
摘要： Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.
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公开(公告)号：US20210335410A1
公开(公告)日：2021-10-28
申请号：US16860498
申请日：2020-04-28
IPC分类号： G11C11/22 , G11C11/4096 , G11C11/4094 , G11C29/04
摘要： Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.
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公开(公告)号：US20210304835A1
公开(公告)日：2021-09-30
申请号：US16835051
申请日：2020-03-30
发明人： Yoshinori Fujiwara
摘要： Apparatuses, systems, and methods for self-test mode abort circuit. Memory devices may enter a self-test mode and perform testing operations on the memory array. During the self-test mode, the memory device may ignore external communications. The memory includes an abort circuit which may terminate the self-test mode if it fails to properly finish. For example, the abort circuit may count an amount of time since the self-test mode began and end the self-test mode if that amount of time meets or exceeds a threshold, which may be based off of the expected amount of time for the testing operations to complete.
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公开(公告)号：US11081166B1
公开(公告)日：2021-08-03
申请号：US17000202
申请日：2020-08-21
发明人： Kevin G. Werhane , Jason M. Johnson , Yoshinori Fujiwara , Tyrel Z. Jensen , Daniel S. Miller , David E. Jefferson , Vivek Kotti
IPC分类号： G11C11/408 , G11C11/22
摘要： Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.
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公开(公告)号：US20210055981A1
公开(公告)日：2021-02-25
申请号：US16545721
申请日：2019-08-20
发明人： Daniel S. Miller , Kevin G. Werhane , Yoshinori Fujiwara , Christopher G. Wieduwilt , Jason M. Johnson , Minoru Someya
摘要： An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.
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