公开(公告)号：US20240241736A1

公开(公告)日：2024-07-18

申请号：US18621898

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F9/448 ,  G06F13/12 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4498 ,  G06F13/126 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/38 ,  G06F13/4282

Abstract: A system includes a primary device comprising a first state machine lattice comprising a first plurality of configurable elements configured to analyze at least a portion of first data as a first analysis and to output a result of the first analysis. The system also includes a secondary device coupled to the primary device, wherein the secondary device comprises a second plurality of configurable elements configured to analyze at least a portion of second data received from the primary device as a second analysis and to output a result of the second analysis, wherein the primary device

公开(公告)号：US11977977B2

公开(公告)日：2024-05-07

申请号：US16917221

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06N3/08 ,  G06N3/063 ,  G06V10/94

CPC classification number: G06N3/08 ,  G06N3/063 ,  G06V10/955

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

公开(公告)号：US11947979B2

公开(公告)日：2024-04-02

申请号：US17736399

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F13/16 ,  G06F9/448 ,  G06F13/12 ,  G06F13/28 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4498 ,  G06F13/126 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/38 ,  G06F13/4282

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

公开(公告)号：US20240012787A1

公开(公告)日：2024-01-11

申请号：US18371635

申请日：2023-09-22

Applicant: Micron Technology, Inc.

Inventor： Harold B. Noyes ,  David R. Brown

IPC: G06F15/78 ,  G06F18/10

CPC classification number: G06F15/78 ,  G06F18/10

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition pr

公开(公告)号：US20220148645A1

公开(公告)日：2022-05-12

申请号：US17091969

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  David R. Brown

IPC: G11C11/406 ,  G06F3/06

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

公开(公告)号：US11226926B2

公开(公告)日：2022-01-18

申请号：US16884302

申请日：2020-05-27

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F15/80 ,  H03K19/17728 ,  G06F16/903 ,  G06K9/00 ,  G06N5/00

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

公开(公告)号：US10949290B2

公开(公告)日：2021-03-16

申请号：US16547241

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

公开(公告)号：US10915450B2

公开(公告)日：2021-02-09

申请号：US16513418

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit Singh Bains

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0875 ,  G06F9/448 ,  G06N3/02

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

公开(公告)号：US10769099B2

公开(公告)日：2020-09-08

申请号：US15534994

申请日：2015-12-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Paul D. Dlugosch

IPC: H04J3/04 ,  G06F15/78 ,  G06N20/00 ,  G06F9/448 ,  G06F1/3225 ,  G06F13/42 ,  G05B19/045 ,  G06F3/06

Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.

公开(公告)号：US10684983B2

公开(公告)日：2020-06-16

申请号：US15137877

申请日：2016-04-25

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F15/80 ,  H03K19/17728 ,  G06F16/903 ,  G06K9/00 ,  G06N5/00

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.