公开(公告)号：US09832860B2

公开(公告)日：2017-11-28

申请号：US14498958

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert Starkston ,  John Guzek ,  Patrick Nardi ,  Keith Jones ,  Javier Soto Gonzalez

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/16 ,  H01L23/498 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/0271 ,  H01L23/16 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/284 ,  H05K2201/09136 ,  H05K2201/10977 ,  H05K2201/2009

Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.

公开(公告)号：US09642248B2

公开(公告)日：2017-05-02

申请号：US14618235

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC: H05K1/00 ,  H05K1/03 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H05K3/46 ,  H01L21/56 ,  H01L21/48 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.