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    DATA TRANSFER USING A DESCRIPTOR
    31.
    发明申请
    DATA TRANSFER USING A DESCRIPTOR 有权
    使用描述符进行数据传输

    公开(公告)号：US20150154131A1

    公开(公告)日：2015-06-04

    申请号：US14551798

    申请日：2014-11-24

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: G06F13/28 ,  G06F12/08

    CPC classification number: G06F13/28 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/1024 ,  G06F2212/6042

    Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

    Abstract translation: 数据处理装置包括多个处理器核，共享处理器高速缓存，总线单元和总线控制器。 共享处理器高速缓存连接到每个处理器内核和主存储器。 总线单元通过总线控制器连接到共享处理器高速缓存器，用于向/从I / O设备传送数据。 为了进一步改进处理器高速缓存和I / O设备之间的数据传输速率，总线控制器被配置为响应于从处理器核心接收到描述符来执行对共享处理器高速缓存的直接存储器访问 根据描述符，经由总线单元将数据从共享处理器高速缓存传送到I / O设备。

    WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES
    32.
    发明申请
    WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES 有权
    在单端口存储器件中写入和读取冲突避免

    公开(公告)号：US20150149727A1

    公开(公告)日：2015-05-28

    申请号：US14090347

    申请日：2013-11-26

    Applicant: International Business Machines Corporation

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: G06F12/08

    CPC classification number: G06F12/0848 ,  G06F12/0846 ,  G11C7/22 ,  G11C11/419 ,  G11C2207/2209

    Abstract: A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.

    Abstract translation: 描述了避免来自两个独立写入操作的单端口存储器设备中的写入冲突的方法。 来自第一写入操作的第一数据对象被划分为第一偶数子数据对象和第一奇数子数据对象。 来自第二写入操作的第二数据对象被划分为第二偶数子数据对象和第二奇数子数据对象。 当第一次写入操作和第二次写入操作同时发生时，第一偶数子数据对象被存储到第一单个端口存储器设备，而第二个奇数子数据对象被存储到第二单个端口存储器设备。 当第一写入操作和第二写入操作同时发生时，第二偶数子数据对象被存储到第一单个端口存储器件和第一奇数子数据对象到第二单个端口存储器件。

    DIRECTED INTERRUPT VIRTUALIZATION WITH RUNNING INDICATOR
    33.
    发明申请
    DIRECTED INTERRUPT VIRTUALIZATION WITH RUNNING INDICATOR 有权

    公开(公告)号：US20220004412A1

    公开(公告)日：2022-01-06

    申请号：US17482514

    申请日：2021-09-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Marco Kraemer ,  Christoph Raisch ,  Bernd Nerz ,  Donald William Schmidt ,  Matthias Klein ,  Sascha Junghans ,  Peter Dana Driever

    IPC: G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54

    Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

    Data transfer using a descriptor
    34.
    发明授权
    Data transfer using a descriptor 有权

    公开(公告)号：US10936517B2

    公开(公告)日：2021-03-02

    申请号：US16451650

    申请日：2019-06-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: G06F12/084 ,  G06F13/28 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0871

    Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

    Data transfer using a descriptor
    37.
    发明授权
    Data transfer using a descriptor 有权

    公开(公告)号：US10394733B2

    公开(公告)日：2019-08-27

    申请号：US15661031

    申请日：2017-07-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: G06F12/084 ,  G06F13/28 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0871

    Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

    Tracing data from an asynchronous interface
    39.
    发明授权
    Tracing data from an asynchronous interface 有权

    公开(公告)号：US09606891B2

    公开(公告)日：2017-03-28

    申请号：US14733249

    申请日：2015-06-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: H04L7/02 ,  H04L7/00 ,  G06F11/34 ,  G06F11/30

    CPC classification number: G06F11/348 ,  G06F11/3027 ,  G06F11/349 ,  G06F2201/86 ,  H04L7/0045 ,  H04L7/02

    Abstract: An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.

    Dynamic evaluation and adaption of hardware hash functions
    40.
    发明授权
    Dynamic evaluation and adaption of hardware hash functions 有权
    硬件哈希函数的动态评估和适应

    公开(公告)号：US09594694B2

    公开(公告)日：2017-03-14

    申请号：US14993583

    申请日：2016-01-12

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Sascha Junghans ,  Matthias Klein ,  Thomas Schlipf

    IPC: G06F3/00 ,  G06F12/10 ,  G06F9/38 ,  G06F1/16 ,  G06F1/03

    CPC classification number: G06F7/544 ,  G06F1/0328 ,  G06F1/1615 ,  G06F7/57 ,  G06F9/3838 ,  G06F12/1018 ,  G06F17/30109 ,  G06F17/30949 ,  G06F2212/401

    Abstract: Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

    Abstract translation: 基于输入向量的位值创建哈希值。 一种装置包括第一和第二散列表，第一和第二散列函数发生器，其适于基于输入向量的位值来配置用于创建第一和第二散列值的相应散列函数。 哈希值存储在相应的散列表中。 评估单元包括比较单元，用于比较第一散列函数和第二散列函数的相应有效性，以及响应于比较单元的交换单元，适于通过第二散列函数来替换第一散列函数。

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