公开(公告)号：US09337200B2

公开(公告)日：2016-05-10

申请号：US14087819

申请日：2013-11-22

Applicant: International Business Machines Corporation

Inventor： Herbert L. Ho ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

IPC: H01L27/10 ,  H01L27/108 ,  H01L29/417 ,  H01L21/762 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L27/10867 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/66181 ,  H01L29/945

Abstract: After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor.

Abstract translation: 在体半导体衬底的上部形成半导体鳍片之后，形成浅沟槽隔离层，其包括电介质材料并且横向围绕每个半导体鳍片的下部。 沟槽形成在相邻的半导体鳍片对的纵向侧壁之间。 横向围绕每个沟槽的浅沟槽隔离层的部分提供了掩埋板和存取晶体管之间的电隔离。 可以通过蚀刻覆盖每个沟槽的一部分和对应的存取晶体管的源极区域的通孔，并且用导电材料填充通孔腔来形成带结构。 沟槽顶部氧化物结构将每个沟槽电容器的内部电极与用于接入鳍场效应晶体管的上覆栅极线电隔离。

公开(公告)号：US09252053B2

公开(公告)日：2016-02-02

申请号：US14157125

申请日：2014-01-16

Applicant: International Business Machines Corporation

Inventor： Rosa A. Orozco-Teran ,  Ravikumar Ramachandran ,  John A. Fitzsimmons ,  Russell H Arndt ,  David L. Rath

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/45 ,  H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/28079 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在第一金属层的顶部上形成具有第一金属层和多个电介质层的半导体结构; 通过所述多个电介质层产生一个或多个开口以暴露所述多个电介质层下面的所述第一金属层; 使所述一个或多个开口向下扩展到所述第一金属层中并且水平地扩展到所述多个介电层下面的区域中; 在所述多个电介质层内的所述一个或多个开口的衬里侧壁中施加一层衬里材料; 并用导电材料填充膨胀的一个或多个开口。

公开(公告)号：US20150249015A1

公开(公告)日：2015-09-03

申请号：US14707822

申请日：2015-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/28

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

公开(公告)号：US20150228749A1

公开(公告)日：2015-08-13

申请号：US14696015

申请日：2015-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

公开(公告)号：US20150035073A1

公开(公告)日：2015-02-05

申请号：US13959375

申请日：2013-08-05

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

Abstract translation: 一种用于半导体制造的方法包括在栅腔中的介电层上形成扩散阻挡层和含金属层中的至少一个。 执行第一退火以将元件从扩散阻挡层和含金属层中的至少一个扩散到电介质层中。 去除含金属层和扩散阻挡层。 执行第二次退火以调节介电层中的元件的扩散以提供栅极电介质区域。

公开(公告)号：US08928057B2

公开(公告)日：2015-01-06

申请号：US13689924

申请日：2012-11-30

Applicant: International Business Machines Corporation

Inventor： William Cote ,  Johnathan E. Faltermeier ,  Babar A. Khan ,  Ravikumar Ramachandran ,  Theodorus E. Standaert ,  Xinhui Wang

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/945 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66181 ,  H01L29/66545

Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

Abstract translation: 一种方法，包括提供从半导体衬底蚀刻并被氧化物层和氮化物层覆盖的散热片，所述氧化物层位于所述散热片和所述氮化物层之间，去除所述翅片的一部分以形成开口，形成介电隔离物 开口的侧壁，并用填充材料填充开口，其中填充材料的顶表面基本上与氮化物层的顶表面齐平。 该方法还可以包括形成与其中一个鳍片成直角的深沟槽电容器，去除氮化物层以在散热片和填充材料之间形成间隙，其中填充材料具有在间隙上延伸的重新排列的几何形状，以及 去除重入的几何形状并使翅片和填充材料之间的间隙变宽。

公开(公告)号：US08912607B2

公开(公告)日：2014-12-16

申请号：US13789018

申请日：2013-03-07

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

IPC: H01L21/70 ,  H01L27/092 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

Abstract translation: 可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。 此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。 在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。 图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。 导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

公开(公告)号：US08829617B2

公开(公告)日：2014-09-09

申请号：US13689948

申请日：2012-11-30

Applicant: International Business Machines Corporation

Inventor： Balasubramanian S. Haran ,  Sanjay Mehta ,  Shom Ponoth ,  Ravikumar Ramachandran ,  Stefan Schmitz ,  Theodorus E. Standaert

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/336

CPC classification number: H01L29/42364 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.

Abstract translation: 一种方法，包括提供从半导体衬底蚀刻并被氧化物层和氮化物层覆盖的多个散热片，所述氧化物层位于所述多个散热片和所述氮化物层之间，去除所述多个翅片的一部分以形成 打开并在开口的侧壁上形成电介质间隔物。 该方法还可以包括用填充材料填充开口，其中填充材料的顶表面基本上与氮化物层的顶表面齐平，去除氮化物层以在多个翅片和填充材料之间形成间隙 ，其中所述填充材料具有在所述间隙上延伸的重新排列的几何形状，以及移除所述重新进入的几何形状并使所述多个翅片和所述填充材料之间的间隙变宽。

公开(公告)号：US20130175635A1

公开(公告)日：2013-07-11

申请号：US13780003

申请日：2013-02-28

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Michael P. Chudzik ,  Ravikumar Ramachandran

IPC: H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/823842

Abstract: A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.

Abstract translation: 在替换金属栅极方案中沉积阻挡金属层和第一型功函数金属层的堆叠。 阻挡金属层可以直接沉积在栅极介电层上。 图案化第一型功函数金属层仅存在于第一类场效应晶体管的区域中。 第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的势垒金属层上。 或者，第一类功函数层可以直接沉积在栅介电层上。 图案化阻挡金属层仅存在于第一类场效应晶体管的区域中。 第二类型功函数金属层直接沉积在第二类场效应晶体管的区域中的栅介质层上。 导电材料填充和平坦化形成双功能功能替代栅极结构。

公开(公告)号：US20240105769A1

公开(公告)日：2024-03-28

申请号：US17935992

申请日：2022-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shahab Siddiqui ,  Ruqiang Bao ,  Charlotte DeWan Adams ,  Curtis S. Durfee ,  Anthony I. Chou ,  Barry Paul Linder ,  Ravikumar Ramachandran ,  Dechao Guo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.