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    PHASE CHANGE MEMORY CELL WITH A METAL LAYER
    31.
    发明申请
    PHASE CHANGE MEMORY CELL WITH A METAL LAYER 有权

    公开(公告)号：US20210159405A1

    公开(公告)日：2021-05-27

    申请号：US16691646

    申请日：2019-11-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Carl Radens ,  Kangguo Cheng ,  JUNTAO LI ,  Ruilong Xie

    IPC: H01L45/00

    Abstract: A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening.

    Vertical gate all-around transistor
    33.
    发明授权
    Vertical gate all-around transistor 有权

    公开(公告)号：US10950722B2

    公开(公告)日：2021-03-16

    申请号：US14588337

    申请日：2014-12-31

    Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： John H. Zhang ,  Carl Radens ,  Lawrence A. Clevenger ,  Yiheng Xu

    IPC: H01L29/78 ,  H01L29/165 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

    Trench interconnect having reduced fringe capacitance
    37.
    发明授权
    Trench interconnect having reduced fringe capacitance 有权
    具有降低的边缘电容的沟槽互连

    公开(公告)号：US09214429B2

    公开(公告)日：2015-12-15

    申请号：US14098346

    申请日：2013-12-05

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

    Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

    TRENCH INTERCONNECT HAVING REDUCED FRINGE CAPACITANCE
    38.
    发明申请
    TRENCH INTERCONNECT HAVING REDUCED FRINGE CAPACITANCE 有权
    具有减少的FRINGE电容的TRENCH INTERCONNECT

    公开(公告)号：US20150162278A1

    公开(公告)日：2015-06-11

    申请号：US14098346

    申请日：2013-12-05

    Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

    Inventor： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

    IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

    Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

    Electrostatic discharge devices for integrated circuits
    39.
    发明授权
    Electrostatic discharge devices for integrated circuits 有权
    用于集成电路的静电放电装置

    公开(公告)号：US08970004B2

    公开(公告)日：2015-03-03

    申请号：US13725666

    申请日：2012-12-21

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

    IPC: H01L29/00 ,  H01L27/02 ,  H01L21/266

    CPC classification number: H01L27/0248 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/0255

    Abstract: A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.

    Abstract translation: 公开了用于保护集成电路免受静电放电的结二极管阵列。 结二极管集成了各种尺寸和功能的对称和非对称结二极管。 一些结二极管被配置为通过未封装的互连线提供低电压和电流放电，而其它结构二极管被配置为通过封装的互连线提供高电压和电流放电。 结二极管阵列元件包括p-n结二极管和N + / N + +结二极管。 结二极管包括具有定制形状的植入区域。 如果不需要对称和非对称二极管作为结二极管阵列的组件，则阵列配置有任一类型的二极管之间的隔离区域。 一些结二极管阵列包括掩埋氧化物层，以防止掺杂剂扩散到超过选定深度的衬底中。

    MODULAR FUSES AND ANTIFUSES FOR INTEGRATED CIRCUITS
    40.
    发明申请
    MODULAR FUSES AND ANTIFUSES FOR INTEGRATED CIRCUITS 有权
    用于集成电路的模块式熔断器和防爆装置

    公开(公告)号：US20150002213A1

    公开(公告)日：2015-01-01

    申请号：US13931692

    申请日：2013-06-28

    Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

    Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

    IPC: H01L23/525 ,  H01F17/02 ,  H01L49/02

    CPC classification number: H01L23/5256 ,  H01F17/0006 ,  H01F17/02 ,  H01F2017/0073 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/5252 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

    Abstract translation: 公开了纳米级电子元件，反熔丝和平面线圈电感器。 铜镶嵌工艺可用于制造所有这些电路元件。 可以使用低温铜蚀刻工艺来制造efuse和efuse样电感器。 电路元件可以通过以不同的配置和尺寸连接金属柱的矩阵来以模块化方式设计和构造。 金属柱的数量，或包括在电路元件中的电介质网的尺寸确定其电特性。 或者，电极和电感器可以由沉积在电介质柱的基体中的间隙金属形成，或者在蚀刻金属块中的柱状开口之后留下。 金属列的阵列还具有第二功能，作为可以改善抛光均匀性以代替常规虚拟结构的特征。 使用这种模块化阵列为集成电路设计人员提供了灵活性。

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