知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.02 seconds)

    Deep trench capacitors embedded in package substrate
    31.
    发明授权
    Deep trench capacitors embedded in package substrate 有权

    公开(公告)号：US12238940B2

    公开(公告)日：2025-02-25

    申请号：US18244716

    申请日：2023-09-11

    Applicant: Google LLC

    Inventor： Nam Hoon Kim ,  Teckgyu Kang ,  Scott Lee Kirkman ,  Woon-Seong Kwon

    IPC: H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/16 ,  H10D1/68

    Abstract: This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.

    Socket To Support High Performance Multi-die ASICs
    34.
    发明公开
    Socket To Support High Performance Multi-die ASICs 审中-公开

    公开(公告)号：US20240096859A1

    公开(公告)日：2024-03-21

    申请号：US17993240

    申请日：2022-11-23

    Applicant: Google LLC

    Inventor： Nam Hoon Kim ,  Jaesik Lee ,  Woon-Seong Kwon ,  Teckgyu Kang

    IPC: H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

    CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/50

    Abstract: A microelectronic system may include a microelectronic component having electrically conductive elements exposed at a first surface thereof, a socket mounted to a first surface of the microelectronic component and including a substrate embedded therein, one or more microelectronic elements each having active semiconductor devices therein and each having element contacts exposed at a front face thereof, and a plurality of socket pins mounted to and extending above the substrate, the socket pins being ground shielded coaxial socket pins. The one or more microelectronic elements may be disposed at least partially within a recess defined within the socket. The socket may have a land grid array comprising top surfaces of the plurality of the socket pins or electrically conductive pads mounted to corresponding ones of the socket pins, and the element contacts of the one or more microelectronic elements may be pressed into contact with the land grid array.

    Temperature Control Element Utilized in Device Die Packages
    38.
    发明公开
    Temperature Control Element Utilized in Device Die Packages 审中-公开

    公开(公告)号：US20230163048A1

    公开(公告)日：2023-05-25

    申请号：US17570647

    申请日：2022-01-07

    Applicant: Google LLC

    Inventor： Yingying Wang ,  Emad Samadiani ,  Madhusudan K. Iyengar ,  Padam Jain ,  Xiaojin Wei ,  Teckgyu Kang ,  Sudharshan Sugavanesh Udhayakumar ,  Yingshi Tang

    IPC: H01L23/46 ,  H01L21/56

    CPC classification number: H01L23/46 ,  H01L21/56 ,  H01L24/73

    Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may assist temperature control of the IC die when in operation. In one example, the temperature control element may have a plurality of thermal dissipating features disposed on a first surface of the IC die to efficiently control and dissipate the thermal energy from the IC die when in operation. A second surface opposite to the first surface of the IC die may include a plurality of devices, such as semiconductors transistors, devices, electrical components, circuits, or the like, that may generate thermal energy when in operation. The temperature control element may provide an IC die with high efficiency of heat dissipation that is suitable for 3D IC package structures and requirements.

    ASIC PACKAGE WITH PHOTONICS AND VERTICAL POWER DELIVERY
    40.
    发明申请
    ASIC PACKAGE WITH PHOTONICS AND VERTICAL POWER DELIVERY 有权

    公开(公告)号：US20210074677A1

    公开(公告)日：2021-03-11

    申请号：US16567766

    申请日：2019-09-11

    Applicant: Google LLC

    Inventor： Woon-Seong Kwon ,  Namhoon Kim ,  Teckgyu Kang ,  Ryohei Urata

    IPC: H01L25/065 ,  G02B6/42 ,  H01L23/538 ,  H01L23/498

    Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

Patent Agency Ranking