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31.发明授权公开(公告)号：US09166680B2
公开(公告)日：2015-10-20
申请号：US14027445
申请日：2013-09-16
Inventor： Chun Ju Youn , Jong-Hoi Kim , Joong-Seon Choe , Duk Jun Kim , Yong-Hwan Kwon , Eun Soo Nam
IPC: H04B10/073 , H04B10/61 , H04L27/22 , H04L27/36 , H04L27/00
CPC classification number: H04B10/0731 , H04B10/613 , H04L27/223 , H04L27/364 , H04L2027/0083
Abstract: Provided is an apparatus and method for measuring IQ imbalance, and in particular, is an apparatus and method for measuring IQ imbalance for an optical receiver. The apparatus for measuring IQ imbalance for an optical receiver includes a light generating unit generating optical and reference signals to provide the optical and reference signals to an optical receiver, a graph creating unit creating a Lissajous figure by using an in-phase (I) signal and a quadrature-phase (Q) signal output from the optical receiver in response to the optical and reference signals, and a calculating unit calculating IQ imbalance for the optical receiver with reference to the Lissajous figure.
Abstract translation: 提供了一种用于测量IQ不平衡的装置和方法，特别是用于测量光接收机的IQ不平衡的装置和方法。 用于测量光接收机的IQ不平衡的装置包括产生光学和参考信号以向光学接收器提供光学参考信号的光产生单元，通过使用同相（I）信号产生李萨如图的图形创建单元 以及响应于光学参考信号从光学接收器输出的正交相位（Q）信号，以及计算单元，参考利萨如图来计算光学接收机的IQ不平衡。
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公开(公告)号：US08937002B2
公开(公告)日：2015-01-20
申请号：US14230031
申请日：2014-03-31
Inventor： Sung Bum Bae , Eun Soo Nam , Jae Kyoung Mun , Sung Bock Kim , Hae Cheon Kim , Chull Won Ju , Sang Choon Ko , Jong-Won Lim , Ho Kyun Ahn , Woo Jin Chang , Young Rak Park
IPC: H01L21/20 , H01L29/66 , H01L21/8252 , H01L27/06 , H01L27/088 , H01L21/02
CPC classification number: H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。
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33.发明授权公开(公告)号：US08841154B2
公开(公告)日：2014-09-23
申请号：US13916006
申请日：2013-06-12
Inventor： Hyung Sup Yoon , Byoung-Gue Min , Jong-Won Lim , Ho Kyun Ahn , Jong Min Lee , Seong-il Kim , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H01L21/28008 , H01L21/28587 , H01L29/42316 , H01L29/66863
Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced. The method of manufacturing a field effect type compound semiconductor device includes: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa region in predetermined regions of the first oxide layer, the ohmic layer, and the active layer; planarizing the mesa region after forming a nitride layer by evaporating a nitride on the mesa region; forming an ohmic electrode on the first oxide layer; forming a minute gate resist pattern after forming a second oxide layer on a semiconductor substrate in which the ohmic electrode is formed and forming a minute gate pattern having a under-cut shaped profile by dry-etching the first oxide layer, the nitride layer, and the second oxide layer; forming a gate recess region by forming a head pattern of a gamma gate electrode on the semiconductor substrate; and forming the gamma gate electrode by evaporating refractory metal on the semiconductor substrate in which the gate recess region is formed.
Abstract translation: 公开了一种制造场效应型化合物半导体器件的方法，其中器件的漏电流降低并且击穿电压增强。 制造场效应型化合物半导体器件的方法包括：在衬底上堆叠有源层和欧姆层，并在欧姆层上形成第一氧化物层; 在所述第一氧化物层，所述欧姆层和所述有源层的预定区域中形成台面区域; 通过在台面区域上蒸发氮化物，在形成氮化物层之后使台面区域平坦化; 在所述第一氧化物层上形成欧姆电极; 在形成欧姆电极的半导体衬底上形成第二氧化物层之后形成微小栅极抗蚀剂图案，并通过干蚀刻第一氧化物层，氮化物层和形成具有下切形状轮廓的微小栅极图案 第二氧化物层; 通过在所述半导体衬底上形成伽马栅电极的头部图形来形成栅极凹部区域; 以及通过在形成有所述栅极凹部的所述半导体衬底上蒸发难熔金属而形成所述γ栅电极。
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公开(公告)号：US20140240691A1
公开(公告)日：2014-08-28
申请号：US13916250
申请日：2013-06-12
Inventor： Bongki MHEEN , MyoungSook Oh , Kisoo Kim , Jae-Sik Sim , Yong-Hwan Kwon , Eun Soo Nam
IPC: G01S17/89
CPC classification number: G01S17/89 , G01S7/4815 , G01S7/4818 , G01S7/484 , G01S7/4863
Abstract: Disclosed are a laser radar system and a method for acquiring an image of a target, and the laser radar system includes: a beam source to emit the laser beam; a beam deflector disposed between the beam source and the target, and configured to deflect the laser beam emitted from the beam source in a scanning direction of the target as time elapses; and an optical detector configured to detect the laser beam reflected from the target, which is provided a plurality of beam spots having a diameter DRBS; and a receiving optical system disposed between the target and the optical detector and configured to converge the laser beam reflected from the target, and the optical detector includes a detecting area having a diameter DDA that satisfies an equation of √{square root over (/2)}×PRBS+2×DRBS≦DDA≦2×Dlens and an equation of (4/π)×λ×F_number
Abstract translation: 公开了一种用于获取目标图像的激光雷达系统和方法，并且激光雷达系统包括：发射激光束的光束源; 光束偏转器，设置在所述光束源和所述目标之间，并且被配置为随着时间的过去使从所述光束源发射的激光束沿所述目标的扫描方向偏转; 以及光检测器，被配置为检测从所述目标物反射的激光束，所述激光束设置有多个具有直径DRBS的光束点; 以及接收光学系统，设置在所述目标和所述光学检测器之间并且被配置为会聚从所述目标物反射的所述激光束，并且所述光学检测器包括具有直径DDA的检测区域，所述检测区域满足以下等式：√{平方根超过（/ 2 ）}×PRBS + 2×DRBS＆nlE; DDA＆nlE; 2×Dlens和（4 /＆pgr;）×λ×F_number
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公开(公告)号：US20140179088A1
公开(公告)日：2014-06-26
申请号：US13897706
申请日：2013-05-20
Inventor： Sung-Bum BAE , Sung Bock Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/02
CPC classification number: H01L21/0254 , H01L21/02458 , H01L21/02496 , H01L21/0262 , H01L21/02664 , H01L21/32
Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.
Abstract translation: 本发明构思提供了制造半导体衬底的方法。 该方法可以包括形成围绕衬底的边缘的停止图案，在除了停止图案之外的基板的整个顶表面上形成过渡层，以及在过渡层和停止图案上形成外延半导体层。 外延半导体层可能不会从停止图案生长。 也就是说，外延半导体层可以通过选择性各向同性生长方法从过渡层的顶表面和侧壁各向同性地生长，使得外延半导体层可以逐渐覆盖停止图案。
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Patent Agency Ranking
公开(公告)号：US08759204B1
公开(公告)日：2014-06-24
申请号：US13897706
申请日：2013-05-20
Inventor： Sung-Bum Bae , Sung Bock Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/20
CPC classification number: H01L21/0254 , H01L21/02458 , H01L21/02496 , H01L21/0262 , H01L21/02664 , H01L21/32
Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.
Abstract translation: 本发明构思提供了制造半导体衬底的方法。 该方法可以包括形成围绕衬底的边缘的停止图案，在除了停止图案之外的基板的整个顶表面上形成过渡层，以及在过渡层和停止图案上形成外延半导体层。 外延半导体层可能不会从停止图案生长。 也就是说，外延半导体层可以通过选择性各向同性生长方法从过渡层的顶表面和侧壁各向同性地生长，使得外延半导体层可以逐渐覆盖停止图案。
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公开(公告)号：US20140167806A1
公开(公告)日：2014-06-19
申请号：US14020931
申请日：2013-09-09
Inventor： Chul Won JU , Hyung Sup Yoon , Jong-Won Lim , Sang-Heung Lee , Seong-il Kim , Dong Min Kang , Eun Soo Nam , Jae Kyoung Mun
IPC: G01R1/04
CPC classification number: G01R1/0466 , G01R1/0458
Abstract: Provided is a semiconductor device testing apparatus including a first socket configured to load a package, on which a semiconductor device to be tested may be mounted, and a second socket coupled to the first socket. The first socket may include an upper part including a hole configured to accommodate the package and a terminal pad provided at both side edges of the hole to hold input and output terminals of the package, and a lower part including a heating room, in which a heater and a temperature sensing part may be provided, the heater being configured to heat the semiconductor device and the temperature sensing part being configured to measure temperature of the semiconductor device. The second socket may include a probe card with a pattern that may be configured to receive test signals from an external power source.
Abstract translation: 提供一种半导体器件测试装置，包括：第一插座，被配置为加载可以安装待测试的半导体器件的封装，以及耦合到第一插座的第二插座。 第一插座可以包括上部，其包括被配置为容纳封装的孔和设置在孔的两个侧边缘处的端子垫，以保持封装的输入和输出端子，以及包括加热室的下部，其中 加热器和温度检测部件，加热器被配置为加热半导体器件，并且温度检测部分被配置为测量半导体器件的温度。 第二插座可以包括具有可被配置为从外部电源接收测试信号的模式的探针卡。
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公开(公告)号：US08697491B2
公开(公告)日：2014-04-15
申请号：US13653068
申请日：2012-10-16
Inventor： Woojin Chang , Soon Il Yeo , Hae Cheon Kim , Eun Soo Nam
IPC: H01L23/053 , H01L21/44
CPC classification number: H01L23/5389 , H01L23/3107 , H01L24/83 , H01L24/90 , H01L25/03 , H01L2224/90 , H01L2924/00011 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2224/83851 , H01L2924/00
Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.
Abstract translation: 提供半导体封装。 半导体封装包括封装体，多个半导体芯片和外部连接端子。 封装体与设置有导电图案和通孔的多个片层叠。 多个半导体芯片被插入到从封装主体的一个表面延伸的插入槽中。 外部连接端子设置在与封装主体的一个表面相对的另一表面上。 这里，多个半导体芯片电连接到外部连接端子。
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39.发明申请公开(公告)号：US20140017885A1
公开(公告)日：2014-01-16
申请号：US13916006
申请日：2013-06-12
Inventor： Hyung Sup YOON , Byoung-gue Min , Jong-Won Lim , Ho Kyun Ahn , Jong Min Lee , Seong-il Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/28
CPC classification number: H01L21/28008 , H01L21/28587 , H01L29/42316 , H01L29/66863
Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced. The method of manufacturing a field effect type compound semiconductor device includes: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa region in predetermined regions of the first oxide layer, the ohmic layer, and the active layer; planarizing the mesa region after forming a nitride layer by evaporating a nitride on the mesa region; forming an ohmic electrode on the first oxide layer; forming a minute gate resist pattern after forming a second oxide layer on a semiconductor substrate in which the ohmic electrode is formed and forming a minute gate pattern having a under-cut shaped profile by dry-etching the first oxide layer, the nitride layer, and the second oxide layer; forming a gate recess region by forming a head pattern of a gamma gate electrode on the semiconductor substrate; and forming the gamma gate electrode by evaporating refractory metal on the semiconductor substrate in which the gate recess region is formed.
Abstract translation: 公开了一种制造场效应型化合物半导体器件的方法，其中器件的漏电流降低并且击穿电压增强。 制造场效应型化合物半导体器件的方法包括：在衬底上堆叠有源层和欧姆层，并在欧姆层上形成第一氧化物层; 在所述第一氧化物层，所述欧姆层和所述有源层的预定区域中形成台面区域; 通过在台面区域上蒸发氮化物，在形成氮化物层之后使台面区域平坦化; 在所述第一氧化物层上形成欧姆电极; 在形成欧姆电极的半导体衬底上形成第二氧化物层之后形成微小栅极抗蚀剂图案，并通过干蚀刻第一氧化物层，氮化物层和形成具有下切形状轮廓的微小栅极图案 第二氧化物层; 通过在所述半导体衬底上形成伽马栅电极的头部图形来形成栅极凹部区域; 以及通过在形成有所述栅极凹部的所述半导体衬底上蒸发难熔金属而形成所述γ栅电极。
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公开(公告)号：US20130169365A1
公开(公告)日：2013-07-04
申请号：US13670016
申请日：2012-11-06
Inventor： Sang-Heung LEE , Seong-Il Kim , Dong Min Kang , Jong-Won Lim , Hyung Sup Yoon , Chull Won Ju , Jae Kyoung Mun , Eun Soo Nam
IPC: H03G3/00
CPC classification number: H03G1/0082 , H03G1/0088 , H03G3/3084
Abstract: Disclosed is an automatic gain control feedback amplifier that can arbitrarily control a gain even when a difference in input signal is large. The automatic gain control feedback amplifier includes: an amplification circuit unit configured to amplify voltage input from an input terminal and output the amplified voltage to an output terminal; a feedback circuit unit connected between the input terminal and the output terminal and including a feedback resistor unit of which a total resistance value is determined by one or more control signals and a feedback transistor connected to the feedback resistor unit in parallel; and a bias circuit unit configured to supply predetermined bias voltage to the feedback transistor.
Abstract translation: 公开了一种自动增益控制反馈放大器，即使当输入信号的差异大时也可以任意地控制增益。 自动增益控制反馈放大器包括：放大电路单元，被配置为放大从输入端输入的电压，并将放大的电压输出到输出端; 连接在输入端子和输出端子之间的反馈电路单元，包括反馈电阻器单元，其总电阻值由一个或多个控制信号确定，反馈晶体管并联连接到反馈电阻器单元; 以及偏置电路单元，被配置为向所述反馈晶体管提供预定的偏置电压。
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