公开(公告)号：US10996555B2

公开(公告)日：2021-05-04

申请号：US16815865

申请日：2020-03-11

Applicant: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Fengli Ji ,  Shanshan Bai ,  Yinan Liang

IPC: G03F1/42 ,  C23C14/04 ,  G03F1/64 ,  B05C17/06 ,  B05C17/08 ,  B05B12/20 ,  H01L21/308 ,  G03F1/66 ,  G03F1/68 ,  H01L51/56 ,  C23C16/04 ,  B05D1/32 ,  H01L51/00

Abstract: A mask frame assembly and an evaporation apparatus are disclosed. The mask frame assembly comprises a frame and a mask plate fixed on the frame. The mask frame assembly is provided with alignment marks, which comprise a first alignment hole arranged in the frame and a second alignment hole arranged in the mask plate. The first alignment hole is a through hole. The mask frame assembly effectively solves a problem in which liquid residuals in alignment holes of the frame interfere with alignment.

公开(公告)号：US10854684B2

公开(公告)日：2020-12-01

申请号：US16234777

申请日：2018-12-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lujiang Huangfu ,  Xiaodan Jin ,  Yinan Liang ,  Zhenzhen Li ,  Wenjing Tan ,  Libin Liu ,  Qian Yang ,  Hongli Wang

IPC: H01L27/32 ,  G09G3/3225 ,  G09G3/3233 ,  H01L51/52

Abstract: A pixel arrangement structure, including a plurality of repeating units, wherein each of the plurality of repeating units includes one first sub-pixel, one second sub-pixel, and two third sub-pixels; in each of the plurality of repeating units, the two third sub-pixels are arranged in one of a first direction and a second direction, and the first sub-pixel and the second sub-pixel are arranged in the other one of the first direction and the second direction; the plurality of repeating units are arranged in the first direction to form a plurality of repeating unit groups, the plurality of repeating unit groups are arranged in the second direction; and the first direction and the second direction are different directions.

公开(公告)号：US10790339B2

公开(公告)日：2020-09-29

申请号：US16094285

申请日：2018-02-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Zhongying Yang ,  Jianpeng Wu ,  Yinan Liang

IPC: H01L27/32 ,  H01L51/56

Abstract: Provided are an OLED array substrate and a manufacturing method thereof, and a display device. The OLED array substrate includes a substrate and a plurality of pixel units provided thereon. The plurality of pixel units are arranged into a plurality of rows extending in a first direction and a plurality of columns extending in a second direction. Each pixel unit includes a plurality of subpixels emitting light of different colors. At least two subpixels emitting light of the same color are adjacent to each other in at least one of the first direction and the second direction.

公开(公告)号：US20180308907A1

公开(公告)日：2018-10-25

申请号：US15578481

申请日：2017-03-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaodan Jin ,  Lujiang Huangfu ,  Yinan Liang

IPC: H01L27/32 ,  H01L51/00 ,  H01L51/56

CPC classification number: H01L27/3218 ,  H01L27/3216 ,  H01L51/001 ,  H01L51/0011 ,  H01L51/56

Abstract: A pixel arrangement structure for a display device. The pixel arrangement structure may comprise a first pixel and a second pixel. The first pixel and the second pixel are alternately in a row direction and a column direction. The first pixel and the second pixel each comprise a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel in the first pixel form a triangular distribution. The first sub-pixel, the second sub-pixel, and the third sub-pixel in the second pixel form an inverted triangular distribution relative to the triangular distribution in the first pixel. The second sub-pixel and the third sub-pixel in each of the first pixel and the second pixel are located on substantially the same row.

公开(公告)号：US09960210B2

公开(公告)日：2018-05-01

申请号：US14908838

申请日：2015-07-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lujiang Huangfu ,  Xiaodan Jin ,  Yinan Liang

IPC: H01L29/04 ,  H01L27/32 ,  G02F1/1362

CPC classification number: H01L27/3218 ,  G02F1/1362 ,  H01L27/32 ,  H01L27/3211 ,  H01L27/3216 ,  H01L27/326

Abstract: The present invention discloses a structure of pixel arrangement and a display device. The structure of pixel arrangement includes a first sub-pixel, and second sub-pixels and third sub-pixels that are provided surrounding the first sub-pixel, the first sub-pixel, portions of the second sub-pixels and portions of the third sub-pixels constituting a virtual rhombus, wherein a center of the first sub-pixel coincides with a center of the virtual rhombus; a center of the second sub-pixel coincides with a first vertex of the virtual rhombus; and a center of the third sub-pixel coincides with a second vertex of the virtual rhombus. Compared with the prior art, the number of sub-pixels required to achieve high resolution display in the present invention is smaller, so that the number of the sub-pixels is decreased.

公开(公告)号：US09947697B2

公开(公告)日：2018-04-17

申请号：US14769891

申请日：2014-09-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yinan Liang ,  Zheng Liu ,  Zuqiang Wang ,  Xueyan Tian

IPC: H01L27/12 ,  H01L27/32

CPC classification number: H01L27/1288 ,  H01L27/1255 ,  H01L27/3262 ,  H01L2227/323

Abstract: The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

公开(公告)号：US09935155B2

公开(公告)日：2018-04-03

申请号：US15031026

申请日：2015-12-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Lujiang Huangfu ,  Yinan Liang ,  Tuo Sun ,  Zhanjie Ma

IPC: H01L29/20 ,  H01L27/32 ,  G09G3/20

CPC classification number: H01L27/3218 ,  G09G3/2003 ,  G09G2300/0452 ,  G09G2300/0465

Abstract: The present disclosure provides a pixel structure, a display panel, and a display apparatus. The pixel structure includes a plurality of pixel cells having a first pixel cell and a first adjacent pixel cell. Each pixel cell includes a first pixel; and two second pixels and two third pixels, surrounding the first pixel. Each of the two second pixels and the two third pixels is arranged separately in a direction along a side of a virtual rectangular area, the first pixel corresponding to one portion of the virtual rectangular area. Each of the two second pixels and the two third pixels has a first portion arranged in the first pixel cell covered by a first virtual rectangular area, and a second portion arranged in the first adjacent pixel cell covered by a second virtual rectangular area.

公开(公告)号：US09761731B2

公开(公告)日：2017-09-12

申请号：US14764307

申请日：2014-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yinan Liang

IPC: H01L27/14 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/283 ,  H01L21/3065 ,  H01L23/31 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/32

CPC classification number: H01L29/78675 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/32139 ,  H01L23/3171 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78633 ,  H01L2227/323

Abstract: A thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The thin film transistor includes a gate electrode, a source electrode, a drain electrode, an active layer and a gate insulation layer. The gate insulation layer is provided above the active layer, the gate, the source electrode and the drain electrode are provided on a same layer above the gate insulation layer, the active layer and the source electrode are connected through a first connection electrode, and the active layer and the drain electrode are connected through a second connection electrode. The thin film transistor can be formed by three times of patterning processes, by which the process time period is shortened, the process yield is improved, and the process cost is reduced, and so on.

公开(公告)号：US20150255170A1

公开(公告)日：2015-09-10

申请号：US14235670

申请日：2013-06-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yinan Liang ,  Lifei Ma ,  Lujiang Huangfu

IPC: G11C19/28 ,  G09G3/32

CPC classification number: G11C19/28 ,  G09G3/3241 ,  G09G2300/043 ,  G09G2310/0286

Abstract: Provided are a threshold voltage compensation circuit of TFT and a method for the same, a shift register and a display device. The threshold voltage compensation circuit includes an input terminal, an output terminal connected to the source of the thin film transistor, a first resistor to a Kth resistor connected in series, and Kth connectable link and at least one first connectable link. Since a voltage dividing circuit having connectable links divides the voltage input to the source of the thin film transistor, such that the gate-source voltage of the thin film transistor can be changed by changing the voltage of the source of the thin film transistor when the voltage of the gate of the thin film transistor is maintained unchanged, so as to control a leakage current of the thin film transistor under a turn-off state, such that the thin film transistor can be turned off normally.

Abstract translation: 提供TFT的阈值电压补偿电路及其方法，移位寄存器和显示装置。 阈值电压补偿电路包括输入端子，连接到薄膜晶体管的源极的输出端子，串联连接的第K个电阻器的第一电阻器和第K个可连接链路和至少一个第一可连接链路。 由于具有可连接链路的分压电路将输入的电压分隔成薄膜晶体管的源极，所以可以通过改变薄膜晶体管的源极的电压来改变薄膜晶体管的栅源电压 薄膜晶体管的栅极的电压保持不变，以便在关断状态下控制薄膜晶体管的漏电流，使得薄膜晶体管可以正常关断。

公开(公告)号：US08987466B2

公开(公告)日：2015-03-24

申请号：US14164668

申请日：2014-01-27

Applicant: BOE Technology Group Co., Ltd. ,  JiLin OLED Material Tech. Co., Ltd.

Inventor： Yinan Liang ,  Xiaoyu Ma ,  Hui Wang ,  Wenyu Ma

IPC: C07F7/08 ,  C07F7/10 ,  H01L51/00

CPC classification number: C07F7/0805 ,  C07F7/0812 ,  H01L51/0058 ,  H01L51/0072 ,  H01L51/0094 ,  H01L51/5012

Abstract: The invention provides a silicon-containing bianthracene derivative, a production process and use thereof, and an organic electroluminescent device. The invention belongs to the technical field of organic electroluminescence, and can give a blue light-emitting material being able to form a dense film. The silicon-containing bianthracene derivative has a molecular structure of the following general formula, wherein R group represents an aryl group having a carbon atom number of 6-14, an aromatic heterocyclic group having a carbon atom number of 8-18, a fused-ring aromatic group having a carbon atom number of 9-15, a fluorenyl group, or a triarylamino group. The silicon-containing bianthracene derivative mentioned in the invention can be used in an organic electroluminescent device.

Abstract translation: 本发明提供含硅的双蒽衍生物，其制备方法及其用途以及有机电致发光器件。 本发明属于有机电致发光技术领域，能够形成能够形成致密膜的蓝色发光材料。 含硅的蒽蒽衍生物具有以下通式的分子结构，其中R基团表示碳原子数为6-14的芳基，碳原子数为8-18的芳族杂环基， 碳原子数为9〜15的芳香族芳基，芴基或三芳基氨基。 本发明中提及的含硅双蒽衍生物可用于有机电致发光器件中。